The motivation of this work is to suggest a guide-line to define a practical overlay metrology requirement for a
given design rule. Total measurement uncertainty, TMU, of an overlay metrology is defined as the square root of square
sum of following items: tool induced shift (TIS)-mean, TIS-3 sigma, dynamic precision, and tool-to-tool match. It is
important to remind that the TMU depends on process conditions, thus TMU is different layer by layer. In this study, the
impact of TMU on overlay error correction, which includes process and measurement noise, is investigated in terms of
the stability of high order overlay correction parameters. By defining the variation range of correctable parameters as a
figure of merit, corresponding TMU is determined for a given design rule. By implementing this methodology, 2 nm of
TMU value is obtained for 45 nm of DRAM half pitch, based upon simulation results. Similarly, 1.0 nm of TMU requirement is suggested for 36 nm of DRAM half pitch. Detailed methodology and simulation results are discussed.