Evaluation of next generation hardware for lithography processing

T. Shimoaoki; M. Enomoto; K. Nafus; H. Marumoto; H. Kosugi; J. Mallmann; R. Maas; C. Verspaget; E. van der Heijden; S. Wang

doi:10.1117/12.846523

30 March 2010 Evaluation of next generation hardware for lithography processing

T. Shimoaoki, M. Enomoto, K. Nafus, H. Marumoto, H. Kosugi, J. Mallmann, R. Maas, C. Verspaget, E. van der Heijden, S. Wang

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Proceedings Volume 7639, Advances in Resist Materials and Processing Technology XXVII; 763922 (2010) https://doi.org/10.1117/12.846523
Event: SPIE Advanced Lithography, 2010, San Jose, California, United States

Abstract

This work is the summary of improvements in processing capability implemented and tested on the LITHIUS Pro^TM -i / TWINSCAN^TM XT:1950Hi litho cluster installed at ASML's development clean room at Veldhoven, the Netherlands. Process performance with regards to CD uniformity (CDU) and defectivity are investigated to confirm adherence to ITRS roadmaps specifications. Specifically, imaging capabilities are tested for 40nm line 80nm pitch with the new bake plate hardware for below hp 3Xnm generation. For defectivity, the combination of Coater/Developer defect reduction hardware with the novel immersion hood design will be tested. For CDU improvements, the enhanced Post Exposure Bake (PEB) plate hardware was verified versus performance of the previous technology plate. Additionally, after the PEB improvement, a remaining across wafer signature was reduced with an optimized develop process. The total CDU budget was analyzed and compared to previous results. Finally the optimized process was applied to a non top coat resist process. For defectivity improvements, the effectiveness of ASML's new immersion hood and TEL's defect reduction hardware were evaluated. The new immersion hood performance was optimal on very hydrophobic materials, which requires optimization of the track hardware and process. The high contact angle materials could be shown to be successfully processed by using TEL's Advanced Defect Reduction (ADR) for residues related to the high contact angle and optimized bevel cut strategy with new bevel rinse hardware. Finally all the optimized processes were combined to obtain defect counts on a highly hydrophobic resist well within manufacturing specifications.

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T. Shimoaoki, M. Enomoto, K. Nafus, H. Marumoto, H. Kosugi, J. Mallmann, R. Maas, C. Verspaget, E. van der Heijden, and S. Wang "Evaluation of next generation hardware for lithography processing", Proc. SPIE 7639, Advances in Resist Materials and Processing Technology XXVII, 763922 (30 March 2010); https://doi.org/10.1117/12.846523

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KEYWORDS

Semiconducting wafers

Photoresist processing

Thin film coatings

Critical dimension metrology

Lithography

Scanning electron microscopy

Manufacturing

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