Litho and patterning challenges for memory and logic applications at the 22-nm node

Jo Finders; Mircea Dusa; Peter Nikolsky; Youri van Dommelen; Robert Watso; Tom Vandeweyer; Joost Beckaert; Bart Laenens; Lieve Van Look

doi:10.1117/12.848330

22 March 2010 Litho and patterning challenges for memory and logic applications at the 22-nm node

Jo Finders, Mircea Dusa, Peter Nikolsky, Youri van Dommelen, Robert Watso, Tom Vandeweyer, Joost Beckaert, Bart Laenens, Lieve Van Look

Author Affiliations +

Proceedings Volume 7640, Optical Microlithography XXIII; 76400C (2010) https://doi.org/10.1117/12.848330
Event: SPIE Advanced Lithography, 2010, San Jose, California, United States

Abstract

In this paper we look into the litho and patterning challenges at the 22nm node. These challenges are different for memory and logic applications driven by the difference in device layout. In the case of memory, very small pitches and CDs have to be printed, close to the optical diffraction limit (k1) and resist resolution capability. For random logic applications e.g. the printing of SRAM, real pitch splitting techniques have to be applied for the first time at the 22nm node due to the aggressive dimensions of extreme small and compact area and pitch of SRAM bitcell. Common challenges are found for periphery of memory and random logic SRAM cells: here the Best Focus difference per feature type, limits the Usable Depth of Focus.

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Jo Finders, Mircea Dusa, Peter Nikolsky, Youri van Dommelen, Robert Watso, Tom Vandeweyer, Joost Beckaert, Bart Laenens, and Lieve Van Look "Litho and patterning challenges for memory and logic applications at the 22-nm node", Proc. SPIE 7640, Optical Microlithography XXIII, 76400C (22 March 2010); https://doi.org/10.1117/12.848330

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