Litho-process-litho for 2D 32nm hp Logic and DRAM double patterning

Patrick Wong; Vincent Wiaux; Staf Verhaegen; Nadia Vandenbroeck

doi:10.1117/12.846998

3 March 2010 Litho-process-litho for 2D 32nm hp Logic and DRAM double patterning

Patrick Wong, Vincent Wiaux, Staf Verhaegen, Nadia Vandenbroeck

Proceedings Volume 7640, Optical Microlithography XXIII; 76400I (2010) https://doi.org/10.1117/12.846998
Event: SPIE Advanced Lithography, 2010, San Jose, California, United States

Abstract

Over the last couple of years a lot of attention has gone to the development of new Litho-Process-Litho-Etch (LPLE) double patterning process alternatives to Litho-Etch-Litho-Etch (LELE) or Spacer-Defined Double Patterning (SDDP)[3,5,6]. Much progress has been made on the material side to improve the resolution of these processes and imaging down to 26nm and even 22 nm 1:1 Lines/Spaces has been demonstrated[1,2,13]. This shows that from a resolution point of view these processes can bridge the gap between ArF immersion single patterning and EUV lithography. These results at small pitches are typically obtained using dipole illumination making them only useful for one pitch-one orientation. Applying the combination of double patterning and dipole illumination is thus limited to regular line/space gratings. For this paper, the patterning of more random 2D and through pitch designs is investigated using the double patterning LPL alternatives for the POLY layer in combination with annular illumination. Fundamental behaviors of the freezing schemes that affect the patterning performance for logic applications are discussed.

Citation Download Citation

Patrick Wong, Vincent Wiaux, Staf Verhaegen, and Nadia Vandenbroeck "Litho-process-litho for 2D 32nm hp Logic and DRAM double patterning", Proc. SPIE 7640, Optical Microlithography XXIII, 76400I (3 March 2010); https://doi.org/10.1117/12.846998

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