4 March 2010 Simulation-based pattern matching using scanner metrology and design data to reduce reliance on CD metrology
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Proceedings Volume 7640, Optical Microlithography XXIII; 764014 (2010); doi: 10.1117/12.848255
Event: SPIE Advanced Lithography, 2010, San Jose, California, United States
Abstract
Scanner matching based on wafer data has proven to be successful in the past years, but its adoption into production has been hampered by the significant time and cost overhead involved in obtaining large amounts of statistically precise wafer CD data. In this work, we explore the possibility of optical model based scanner matching that maximizes the use of scanner metrology and design data and minimizes the reliance on wafer CD metrology. A case study was conducted to match an ASML ArF immersion scanner to an ArF dry scanner for a 6Xnm technology node. We used the traditional, resist model based matching method calibrated with extensive wafer CD measurements and derived a baseline scanner manipulator adjustment recipe. We then compared this baseline scanner-matching recipe to two other recipes that were obtained from the new, optical model based matching method. In the following sections, we describe the implementation of both methods, provide their predicted and actual improvements after matching, and compare the ratio of performance to the workload of the methods. The paper concludes with a set of recommendations on the relative merits of each method for a variety of use cases.
© (2010) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Yuan He, Erik Byers, Scott Light, Danielle Hines, Anton Devilliers, Mike Hyatt, Jianming Zhou, Vinay Nair, Zongchang Yu, Yu Cao, Xu Xie, Wenjin Shao, Rafael Aldana, Ronald Goossens, Chang-Qun Ma, Junwei Lu, Hua-yu Liu, Chris Aquino, Peter Engblom, Tjitte Nooitgedagt, Eric Janda, "Simulation-based pattern matching using scanner metrology and design data to reduce reliance on CD metrology", Proc. SPIE 7640, Optical Microlithography XXIII, 764014 (4 March 2010); doi: 10.1117/12.848255; https://doi.org/10.1117/12.848255
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KEYWORDS
Scanners

Wafer-level optics

Semiconducting wafers

Data modeling

Metrology

Calibration

Critical dimension metrology

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