The 22nm logic node is being approached from at least two different scaling paths. One approach "B" will use Gate and
1x Metal pitches of approximately 80nm, which, combined with the appropriate design style, may allow single exposure
to be used. The other combination under consideration "A" will have a Gate pitch of ~90nm and a 1x Metal pitch of
70nm. Even with immersion scanners, the Rayleigh k1 factor is below 0.32 for 90nm pitch and below the single exposure
resolution limits when the pitch is below 80nm.
Although highly regular gridded patterns help [1,2,3], one of the critical issues for 22nm patterning is Contact and Via
patterning. The lines / cuts approach works well for the poly and interconnect layers, but the "hole" layers have less
benefit from gridded designs and remain a big challenge for patterning.
One approach to reduce the lithography optimization problem is to reconsider the interconnection stack. The Contact
layer is complex because it is connecting two layers on the bottom - Active and Gate - to one layer on the top. Other
layers such as Via-1 only have one layer on the bottom.
A potential solution is a Local Interconnect layer. This layer could be formed as part of the salicide process module,
where a patterned etch would replace the blanket strip of un-reacted metal of the silicide layer. Local interconnect lines
would run parallel to the Gate electrodes, eliminating "wrong-way" lines in the Active layer. Depending on the final
pitch chosen, Local Interconnect could be single or double patterned, or could be done with a self-aligned process plus a
Example layouts of standard cells have shown a significant benefit with local interconnects. For example, the Contact
count is reduced by ~25%, and in many cases Via-1 and Metal-2 usage was eliminated.
The simplified Active pattern, along with reduced contact count and density, permit a different lithography optimization
for the cells designed with Local Interconnect. Metal-1 complexity was also reduced. Details of lithography optimization
results for critical layers, Active, Gate, Local Interconnect, Contact, and Metal-1 will be presented.