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10 March 2010 Challenges for low-k1 lithography in logic devices by source mask co-optimization
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Through simulation and experiment, we evaluate the performance of process window improvement by source only optimization, mask only optimization or source mask co-optimization. From the results, we demonstrate that SMO is the most effective, and free-form source application is also effective. Additionally, it is found that SMO with calibrated resist model is very predictable. We then show that SMO application provides reasonable process window for 28-nm node and 22-nm node.
© (2010) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Kazuyuki Yoshimochi, Seiji Nagahara, Kazuhiro Takeda, and Takayuki Uchiyama "Challenges for low-k1 lithography in logic devices by source mask co-optimization", Proc. SPIE 7640, Optical Microlithography XXIII, 76401K (10 March 2010);

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