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2 April 2010 Modeling and characterization of contact-edge roughness for minimizing design and manufacturing variations in 32-nm node standard cell
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Abstract
Despite intensive attention on line-edge roughness (LER), contact-edge roughness (CER) has been relatively less studied. Contact patterning is one of the critical steps in a state-of-the-art lithography process; meanwhile, the design rule shrinking leads to larger CER in contact holes. Since source/drain (S/D) contact resistance depend on contact area and shape, larger CER results in significant change in a device current. In this paper, we first propose a CER model based on power spectral density function which is a function of RMS edge roughness, correlation length, and fractal dimension. Then, we present a comprehensive contact extraction methodology for analyzing process-induced CER effects on circuit performance. In our new contact extraction model, we first dissect the contact with a same distance, and then calculate the effective resistance considering both the shape weighting factor and the distance weighting factor for stress induced CMOS cells. Using the results of CER, we analyze the impact of CER variation on the S/D contact resistance and the device saturation current. Results show that when the rms value of CER is 10nm, the S/D contact resistance and the device saturation current can vary by as much as 57.8% and 2.1%, respectively.
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Yongchan Ban, Yuansheng Ma, Harry J. Levinson, Yunfei Deng, Jongwook Kye, and David Z. Pan "Modeling and characterization of contact-edge roughness for minimizing design and manufacturing variations in 32-nm node standard cell", Proc. SPIE 7641, Design for Manufacturability through Design-Process Integration IV, 76410D (2 April 2010); https://doi.org/10.1117/12.846654
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