Continuous shrinkage of design rule (DR) in ultra-large-scale integrated circuit (ULSI) devices brings about greater difficulty in the manufacturing process. The keys to meeting small process margin are adequate extraction of critical dimension (CD) tolerance for each object and budgeting the tolerance for each process step.
Furthermore, to extract adequate tolerance, design intent in terms of electrical behavior should be carefully
considered. Electrical behavior is carefully verified in both cell and chip design phases with respect to timing, IR
drop, signal integrity, crosstalk, etc., using various electronic design automation (EDA) tools. However, once the
design data is converted to layout data and signed off, most of the design intention is abandoned and unrecognized
in the process phase. Thus, instead of essential tolerance according to layout-related design intention, uniform and
redundant tolerance is used, and therefore excess tolerance is assigned for some layouts.
To solve the problem described above, a tolerance-based manufacturing system utilizing flexible layout-dependent
speculation derived from design intention has been discussed. In this paper, a test flow is developed and application to 45nm node test chip is examined.