2 April 2010 Demonstrating the benefits of template-based design-technology co-optimization
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The concept of template-based design-technology co-optimization as a means of curbing escalating design complexity and increasing technology qualification risk is described. Data is presented highlighting the design efficacy of this proposal in terms of power, performance, and area benefits, quantifying the specific contributions of complex logic gates in this design optimization. Experimental results from 32nm technology node bulk CMOS wafers are presented to quantify the variability and design-margin reductions as well as yield and manufacturability improvements achievable with the proposed template-based design-technology co-optimization technique. The paper closes with data showing the predictable composability of individual templates, demonstrating a fundamental requirement of this proposal.
© (2010) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Lars Liebmann, Lars Liebmann, Jason Hibbeler, Jason Hibbeler, Nathaniel Hieter, Nathaniel Hieter, Larry Pileggi, Larry Pileggi, Tejas Jhaveri, Tejas Jhaveri, Matthew Moe, Matthew Moe, Vyacheslav Rovner, Vyacheslav Rovner, } "Demonstrating the benefits of template-based design-technology co-optimization", Proc. SPIE 7641, Design for Manufacturability through Design-Process Integration IV, 76410R (2 April 2010); doi: 10.1117/12.848244; https://doi.org/10.1117/12.848244

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