5 May 2010 An analytic formula for determination of simulation runs for analysis of VLSI circuits
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Proceedings Volume 7679, Micro- and Nanotechnology Sensors, Systems, and Applications II; 76792F (2010); doi: 10.1117/12.852500
Event: SPIE Defense, Security, and Sensing, 2010, Orlando, Florida, United States
Abstract
In this article, an explicit formula is derived for determining appropriate number of simulation runs to estimate the parametric yield or violation probability of VLSI circuits. The formula involves no approximation and thus offers a rigorous control of the statistical error of estimation. Moreover, the formula is substantially less conservative than existing methods and hence can be used to avoid unnecessary computation. The application of the formula is illustrated by the timing analysis of an n-input NAND gate with a capacitive load.
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Xinjia Chen, Pradeep Bhattacharya, Ernest Walker, Jiecai Luo, "An analytic formula for determination of simulation runs for analysis of VLSI circuits", Proc. SPIE 7679, Micro- and Nanotechnology Sensors, Systems, and Applications II, 76792F (5 May 2010); doi: 10.1117/12.852500; https://doi.org/10.1117/12.852500
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KEYWORDS
Monte Carlo methods

Computer simulations

Error analysis

Very large scale integration

Statistical analysis

Device simulation

Capacitance

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