30 July 2010 Fundamental performance differences between CMOS and CCD imagers, part IV
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Abstract
This paper is a continuation of past papers written on fundamental performance differences of scientific CMOS and CCD imagers. New characterization results presented below include: 1). a new 1536 × 1536 × 8μm 5TPPD pixel CMOS imager, 2). buried channel MOSFETs for random telegraph noise (RTN) and threshold reduction, 3) sub-electron noise pixels, 4) 'MIM pixel' for pixel sensitivity (V/e-) control, 5) '5TPPD RING pixel' for large pixel, high-speed charge transfer applications, 6) pixel-to-pixel blooming control, 7) buried channel photo gate pixels and CMOSCCDs, 8) substrate bias for deep depletion CMOS imagers, 9) CMOS dark spikes and dark current issues and 10) high energy radiation damage test data. Discussions are also given to a 1024 × 1024 × 16 um 5TPPD pixel imager currently in fabrication and new stitched CMOS imagers that are in the design phase including 4k × 4k × 10 μm and 10k × 10k × 10 um imager formats.
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James Janesick, James Janesick, Jeff Pinter, Jeff Pinter, Robert Potter, Robert Potter, Tom Elliott, Tom Elliott, James Andrews, James Andrews, John Tower, John Tower, Mark Grygon, Mark Grygon, Dave Keller, Dave Keller, } "Fundamental performance differences between CMOS and CCD imagers, part IV", Proc. SPIE 7742, High Energy, Optical, and Infrared Detectors for Astronomy IV, 77420B (30 July 2010); doi: 10.1117/12.862491; https://doi.org/10.1117/12.862491
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