14 September 2010 C to VHDL compiler
Author Affiliations +
Proceedings Volume 7745, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2010; 77451F (2010) https://doi.org/10.1117/12.872194
Event: Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2010, 2010, Wilga, Poland
Abstract
The main goal of C to VHDL compiler project is to make FPGA platform more accessible for scientists and software developers. FPGA platform offers unique ability to configure the hardware to implement virtually any dedicated architecture, and modern devices provide sufficient number of hardware resources to implement parallel execution platforms with complex processing units. All this makes the FPGA platform very attractive for those looking for efficient heterogeneous, computing environment. Current industry standard in development of digital systems on FPGA platform is based on HDLs. Although very effective and expressive in hands of hardware development specialists, these languages require specific knowledge and experience, unreachable for most scientists and software programmers. C to VHDL compiler project attempts to remedy that by creating an application, that derives initial VHDL description of a digital system (for further compilation and synthesis), from purely algorithmic description in C programming language. This idea itself is not new, and the C to VHDL compiler combines the best approaches from existing solutions developed over many previous years, with the introduction of some new unique improvements.
© (2010) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Piotr P Berdychowski, Wojciech M. Zabolotny, "C to VHDL compiler", Proc. SPIE 7745, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2010, 77451F (14 September 2010); doi: 10.1117/12.872194; https://doi.org/10.1117/12.872194
PROCEEDINGS
10 PAGES


SHARE
RELATED CONTENT

Novel MRC algorithms using GPGPU
Proceedings of SPIE (June 29 2012)
FPGA realization of a split radix FFT processor
Proceedings of SPIE (May 10 2007)
Signal processor packaging design
Proceedings of SPIE (October 20 1993)
Development of DSP and FPGA based 4-axis motion controller
Proceedings of SPIE (December 28 2010)

Back to Top