In Si-LSI industry, the variation of device characteristics has been one of the issues because of 10-year-lifetime LSI and
high-yield mass production, and it has been continuously developing the several methods to mitigate and straighten out it.
Currently, the local and random variation has been still the critical issue, compared to the global variation and the
systematic one, because devices are so scaled down and the packing-density of devices is very high in LSI's. In FEOL,
this variation leads to the performance degradation of SRAM, which consists of six transistors in small cells and works
as the main memory on chip. This is because the local and random variation can cause the mismatch of pair transistors.
In BEOL, the variation causes the degradation of interconnect performance and reliability, and leads to the performance
degradation of many circuits. It is suggested that the main mechanism in that variation can be line edge roughness (LER)
and random dopant fluctuation (RDF). Both LER and RDF are related to a lot of process technologies, such as
lithography, etching, annealing and so on. In order to analyze the relationship between this variation and process
technology and to reduce the variation, we should develop the new analysis methods for variations in <50nm CMOS
devices and the new control methods. This paper presents the current status of variations and variation mechanisms, and
discusses future requirements for the advanced CMOS-LSI.