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26 May 2010 Development of computational spacer patterning technology
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Proceedings Volume 7748, Photomask and Next-Generation Lithography Mask Technology XVII; 77480S (2010) https://doi.org/10.1117/12.868940
Event: Photomask and NGL Mask Technology XVII, 2010, Yokohama, Japan
Abstract
Computational spacer patterning technology (SPT) has been developed for the first time to address the challenges concerning hotspots and mask specifications in SPT. A simulation combined with a lithography, etching and deposition model shows the strong correlation of 0.999, 0.993, 0.980 with the experimental critical dimension (CD), mask error-enhancement factor (MEEF) and defect printability through a series of spacer processes, respectively. Furthermore, a design for manufacturability (DfM) flow using computational SPT can find hotspots caused by spacer patterning processes as well as those caused by lithography process and help designers make the circuit layout more robust. Besides, a newly defined MEEF and defect printability, which are primary metrics for mask specification, can be predicted so accurately by using computational SPT that the new scheme to determine appropriate mask specifications is shown to be feasible under the spacer patterning process condition. Thus, computational SPT is found to be promising for addressing the challenges concerning hotspot removal and mask specification in the upcoming 20-30nm node and beyond.
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Hiromitsu Mashita, Takafumi Taguchi, Fumiharu Nakajima, Katsumi Iyanagi, Toshiya Kotani, Shoji Mimotogi, and Soichi Inoue "Development of computational spacer patterning technology", Proc. SPIE 7748, Photomask and Next-Generation Lithography Mask Technology XVII, 77480S (26 May 2010); https://doi.org/10.1117/12.868940
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