Characterization Of Two Level Overlay In X-Ray/Optical Stepper Mix And Match Lithography

J. J. LaBrie; B. Fay; S. Bijawat; M. A. Blanco; K. M. Monahan; J. T. Chen; D. F. Kyser

doi:10.1117/12.940427

17 April 1987 Characterization Of Two Level Overlay In X-Ray/Optical Stepper Mix And Match Lithography

J. J. LaBrie, B. Fay, S. Bijawat, M. A. Blanco, K. M. Monahan, J. T. Chen, D. F. Kyser

Proceedings Volume 0775, Integrated Circuit Metrology, Inspection, & Process Control; (1987) https://doi.org/10.1117/12.940427
Event: Microlithography Conferences, 1987, Santa Clara, CA, United States

Abstract

A practical approach for submicron lithography is mix and match imaging using x-ray and optical steppers. The advantages of x-ray lithography are primarily submicron resolution, unlimited depth of focus and insensitivity to substrate topology and composition. Optical lithography on the other hand becomes most difficult in the submicron region where process latitude becomes tightly limited. It seems reasonable to combine the cost advantage of optical lithography with the technical advantages of x-ray lithography by applying the x-ray technology to critical layers, difficult to image with optical steppers, for example, metal or polysilicon. In this approach, overlay between x-ray and optical levels is the pivotal issue, because it requires achieving an acceptable match between the grid irregularities of the two steppers used. The subject of this presentation is the characterization of a two level overlay in a mix and match lithography experiment involving a 10X optical stepper and a 1X x-ray stepper. Issues of field size differences, placement distortion in the optical and x-ray cases will be discussed. The overlay characterization and optimization method will be presented. Experimental results will be given and discussed.

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J. J. LaBrie, B. Fay, S. Bijawat, M. A. Blanco, K. M. Monahan, J. T. Chen, and D. F. Kyser "Characterization Of Two Level Overlay In X-Ray/Optical Stepper Mix And Match Lithography", Proc. SPIE 0775, Integrated Circuit Metrology, Inspection, & Process Control, (17 April 1987); https://doi.org/10.1117/12.940427

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