Ultra-low power silicon photonic transceivers for inter/intra-chip interconnects

Xuezhe Zheng; John E. Cunningham; Guoliang Li; Ying Luo; Hiren Thacker; Jin Yao; Ron Ho; Jon Lexau; Frankie Liu; Dinesh Patil; Philip Amberg; Nathaniel Pinckney; Po Dong; Dazeng Feng; Mehdi Asghari; Attila Mekis; Thierry Pinguet; Kannan Raj; Ashok V. Krishnamoorthy

doi:10.1117/12.863087

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20 August 2010 Ultra-low power silicon photonic transceivers for inter/intra-chip interconnects

Xuezhe Zheng, John E. Cunningham, Guoliang Li, Ying Luo, Hiren Thacker, Jin Yao, Ron Ho, Jon Lexau, Frankie Liu, Dinesh Patil, Philip Amberg, Nathaniel Pinckney, Po Dong, Dazeng Feng, Mehdi Asghari, Attila Mekis, Thierry Pinguet, Kannan Raj, Ashok V. Krishnamoorthy

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Proceedings Volume 7797, Optics and Photonics for Information Processing IV; 779702 (2010) https://doi.org/10.1117/12.863087
Event: SPIE Optical Engineering + Applications, 2010, San Diego, California, United States

Abstract

Scaling of high performance, many-core, computing systems calls for disruptive solutions to provide ultra energy efficient and high bandwidth density interconnects at very low cost. Silicon photonics is viewed as a promising solution. For silicon photonics to prevail and penetrate deeper into the computing system interconnection hierarchy, it requires innovative optical devices, novel circuits, and advanced integration. We review our recent progress in key building blocks toward sub pJ/bit optical link for inter/intra-chip applications, ultra-low power silicon photonic transceivers. In particular, compact reverse biased silicon ring modulator was developed with high modulation bandwidth sufficient for 15Gbps modulation, very small junction capacitance of ~50fF, low voltage swing of 2V, high extinction ratio (>7dB) and low optical loss (~2dB at on-state). Integrated with low power CMOS driver circuits using low parasitic microsolder bump technique, we achieved record low power consumption of 320fJ/bit at 5Gbps data rate. Stable operation with biterror- rate better than 10^-13was accomplished with simple thermal management. We further review the first hybrid integrated silicon photonic receiver based on Ge waveguide photo detector using the same integration technique, with which high energy efficiency of 690fJ/bit, and sensitivity of ~18.9dBm at 5Gbps data rate for bit-error-rate of 10^-12were achieved.

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Xuezhe Zheng, John E. Cunningham, Guoliang Li, Ying Luo, Hiren Thacker, Jin Yao, Ron Ho, Jon Lexau, Frankie Liu, Dinesh Patil, Philip Amberg, Nathaniel Pinckney, Po Dong, Dazeng Feng, Mehdi Asghari, Attila Mekis, Thierry Pinguet, Kannan Raj, and Ashok V. Krishnamoorthy "Ultra-low power silicon photonic transceivers for inter/intra-chip interconnects", Proc. SPIE 7797, Optics and Photonics for Information Processing IV, 779702 (20 August 2010); https://doi.org/10.1117/12.863087

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