20 August 2010 Comparative study on 3D optical network-on-chip architectures
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Proceedings Volume 7820, International Conference on Image Processing and Pattern Recognition in Industrial Engineering; 78203A (2010) https://doi.org/10.1117/12.867453
Event: International Conference on Image Processing and Pattern Recognition in Industrial Engineering, 2010, Xi'an, China
Abstract
Network-on-chip (NoC) has been proposed to overcome the bottlenecks that on-chip communication faced due to the increase of chip complexity. However, limitations such as long delay and high power consumption make traditional NoC using electronic interconnects be inefficient for future use. A new design concept based on optical interconnects, Optical NoC, which can provide low latency, high bandwidth and lower power dissipation, is a promising solution for future on-chip interconnection. In this paper, we will investigate three different 3D Mesh-based ONoC topologies and compare them in terms of End-to-end delay (ETE delay) and network throughput under varying injection rates. The simulation result shows that 3D Partially-connected Optical-crossbar Mesh can achieve smaller network latency and throughput than other three Mesh based architectures.
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Jun Zhang, Jun Zhang, Huaxi Gu, Huaxi Gu, } "Comparative study on 3D optical network-on-chip architectures", Proc. SPIE 7820, International Conference on Image Processing and Pattern Recognition in Industrial Engineering, 78203A (20 August 2010); doi: 10.1117/12.867453; https://doi.org/10.1117/12.867453
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