4 November 2010 Synthesis arrangement and parity correction of linear array infrared detector
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According to the configuration and technical specification of the detector, which has multiple channels, channels mixing, high speed outputs and separate columns between odd and even, a real time digital processing unit based on the CPLD, FPGA and DSP has been developed to achieve the data synthesis and arrangement function and the parity correction algorithm. A special interface circuit with 4 CPLDs is designed to complete the first synthesis step where the 16 channels of data are combined into 4 channels. The second step is finished in FPGA and ROM address encoder where the 4 channels of data are combined into 1 channel. For output data synchronization, FIFO is adopted to achieve the delay of even channels in the parity correction. Data of odd channels enters the columns synthesis unit without any processing and even channels shall be processed in the columns synthesis unit after entering the FIFO unit first and experiencing the delay process. Thereby the pre-processing before image processing of the linear array thermal imager is accomplished.
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Qun Wang, Qun Wang, Pu Hong, Pu Hong, Bo Wang, Bo Wang, Chensheng Wang, Chensheng Wang, } "Synthesis arrangement and parity correction of linear array infrared detector", Proc. SPIE 7854, Infrared, Millimeter Wave, and Terahertz Technologies, 78541J (4 November 2010); doi: 10.1117/12.869520; https://doi.org/10.1117/12.869520

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