25 January 2011 Highly scalable digital front end architectures for digital printing
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HP's digital printing presses consume a tremendous amount of data. The architectures of the Digital Front Ends (DFEs) that feed these large, very fast presses have evolved from basic, single-RIP (Raster Image Processor) systems to multirack, distributed systems that can take a PDF file and deliver data in excess of 3 Gigapixels per second to keep the presses printing at 2000+ pages per minute. This paper highlights some of the more interesting parallelism features of our DFE architectures. The high-performance architecture developed over the last 5+ years can scale up to HP's largest digital press, out to multiple mid-range presses, and down into a very low-cost single box deployment for low-end devices as appropriate. Principles of parallelism pervade every aspect of the architecture, from the lowest-level elements of jobs to parallel imaging pipelines that feed multiple presses. From cores to threads to arrays to network teams to distributed machines, we use a systematic approach to move bottlenecks. The ultimate goals of these efforts are: to take the best advantage of the prevailing hardware options at our disposal; to reduce power consumption and cooling requirements; and to ultimately reduce the cost of the solution to our customers.
© (2011) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
David Staas, David Staas, "Highly scalable digital front end architectures for digital printing", Proc. SPIE 7872, Parallel Processing for Imaging Applications, 787204 (25 January 2011); doi: 10.1117/12.872021; https://doi.org/10.1117/12.872021


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