16 February 2011 A novel 3D architecture for high-dynamic range image sensor and on-chip data compression
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High Dynamic Range (HDR) Image sensors aim at having a dynamic over 120dB. Compared to classical architectures this is obtained at the cost of a higher transistor count, thus lower fill factor. Three Dimensional integrated circuits (3DIC) somehow change the constraints, photodiodes and electronics can be stacked on different layers, giving more processing powers without compromising the fill factor. In this paper, we propose an original architecture for a high dynamic 3D image sensor with data reduction obtained by local compression. HDR acquisition is based on a floating point coding shared by a group of pixel (macro-pixel), thus giving also a first level of compression. A second level of compression is performed by using a Discrete Cosine Transform (DCT). With this new concept a good image quality (PSNR of about 40 dB) and a high dynamic range (120 dB) are obtained within a pixel area of 5μm×5μm.
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F. Guezzi-Messaoud, F. Guezzi-Messaoud, A. Dupret, A. Dupret, A. Peizerat, A. Peizerat, Y. Blanchard, Y. Blanchard, } "A novel 3D architecture for high-dynamic range image sensor and on-chip data compression", Proc. SPIE 7875, Sensors, Cameras, and Systems for Industrial, Scientific, and Consumer Applications XII, 78750T (16 February 2011); doi: 10.1117/12.872434; https://doi.org/10.1117/12.872434

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