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5 April 2011 Feasibility of EUVL thin absorber mask for sub-32nm half pitch patterning
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Abstract
EUV lithography is the leading candidate for sub-32nm half-pitch device manufacturing. EUV Pre-Production Tool (PPT) is expected to be available at the end of 2010. As EUVL era comes closer, EUVL infrastructure has to get mature including EUVL mask stack. To reduce HV CD bias which comes from shadowing effect, thin mask stack has been considered. We presented that EUVL mask with 58nm absorber height shows same printing performance with conventional EUVL mask with 80nm absorber height in our previous work. CD change and pattern damage at the exposure field edges due to light leakage from the neighboring fields were also demonstrated. In this paper, optimal mask stack which shows lower H-V CD bias than conventional structure using 70-nm-thick absorber is proposed. To find minimized absorber height for sub-32nm pattering experimentally, printing result of conventional mask and thin mask stack with 1:1 L/S patterns will be compared. Further-on, we demonstrate the printing result of the reticle which is designed to minimize CD error at the exposure field edges due to mask black border reflectivity by reducing reflectivity from the absorber. All the wafers are exposed at ASML Alpha Demo Tool (ADT) and Pre-Production Tool (PPT) S-litho EUV is used for simulation.
© (2011) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Yoonsuk Hyun, Juntaek Park, Sunyoung Koo, Yongdae Kim, Seokkyun Kim, Changmoon Lim, Donggyu Yim, and Sungki Park "Feasibility of EUVL thin absorber mask for sub-32nm half pitch patterning", Proc. SPIE 7969, Extreme Ultraviolet (EUV) Lithography II, 79690Y (5 April 2011); doi: 10.1117/12.879371; https://doi.org/10.1117/12.879371
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