8 April 2011 EUV lithography for 22nm half pitch and beyond: exploring resolution, LWR, and sensitivity tradeoffs
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Proceedings Volume 7969, Extreme Ultraviolet (EUV) Lithography II; 79692K (2011); doi: 10.1117/12.879641
Event: SPIE Advanced Lithography, 2011, San Jose, California, United States
The International Technology Roadmap for Semiconductors (ITRS) denotes Extreme Ultraviolet (EUV) lithography as a leading technology option for realizing the 22nm half pitch node and beyond. According to recent assessments made at the 2010 EUVL Symposium, the readiness of EUV materials remains one of the top risk items for EUV adoption. The main development issue regarding EUV resists has been how to simultaneously achieve high resolution, high sensitivity, and low line width roughness (LWR). This paper describes our strategy, the current status of EUV materials, and the integrated post-development LWR reduction efforts made at Intel Corporation. Data collected utilizing Intel's Micro- Exposure Tool (MET) is presented in order to examine the feasibility of establishing a resist process that simultaneously exhibits ≤22nm half-pitch (HP) L/S resolution at ≤11.3mJ/cm2 with ≤3nm LWR.
© (2011) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
E. Steve Putna, Todd R. Younkin, Michael Leeson, Roman Caudillo, Terence Bacuita, Uday Shah, Manish Chandhok, "EUV lithography for 22nm half pitch and beyond: exploring resolution, LWR, and sensitivity tradeoffs", Proc. SPIE 7969, Extreme Ultraviolet (EUV) Lithography II, 79692K (8 April 2011); doi: 10.1117/12.879641; https://doi.org/10.1117/12.879641

Line width roughness

Extreme ultraviolet

Extreme ultraviolet lithography

Photoresist processing

Photoresist developing

Photoresist materials

Materials processing

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