Invited Paper GaAs Self-Aligned MESFET Technologies

Masahiro Hirayama; Tetsuhiko Ikegami

doi:10.1117/12.941056

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22 April 1987 Invited Paper GaAs Self-Aligned MESFET Technologies

Masahiro Hirayama, Tetsuhiko Ikegami

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Proceedings Volume 0797, Advanced Processing of Semiconductor Devices; (1987) https://doi.org/10.1117/12.941056
Event: Advances in Semiconductors and Semiconductor Structures, 1987, Bay Point, FL, United States

Abstract

GaAs self-aligned MESFETs with sub-micron gate were developed using buried p-layer(BP) to suppress short channel effects and applied to LSIs. According to calculation results, 200 to 300 mS/mm transconductance is necessary to realize 100 to 80 ps/gate propagation delay time in 1 k-gate LSIs. A half micron gate length SAINT FET exhibitrd transconductance in excess 200 mS/mm. BP-MESFETs were applied to ICs with operation clock cycles of 2 - Gb/s for about 250 gate scale and 700 Mb/s for 1 k-gate scale. Radiation hardness of 10 rad were tested. Technological advancements in barrier height enlargement related to amorphous silicon, three level interconnection, and rapid thermal annealing are described. In addition, the GaAs MESFET scaling law and estimated transconductance of 850 mS/mm is discussed.

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Masahiro Hirayama and Tetsuhiko Ikegami "Invited Paper GaAs Self-Aligned MESFET Technologies", Proc. SPIE 0797, Advanced Processing of Semiconductor Devices, (22 April 1987); https://doi.org/10.1117/12.941056

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