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17 March 2011 Nanoimprint lithography for semiconductor devices and future patterning innovation
Tatsuhiko Higashiki, Tetsuro Nakasugi, Ikuo Yoneda
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Proceedings Volume 7970, Alternative Lithographic Technologies III; 797003 (2011) https://doi.org/10.1117/12.882940
Event: SPIE Advanced Lithography, 2011, San Jose, California, United States
Abstract
Nanoimprint lithography (NIL) has been expected as a low cost lithography solution as well as pattern shrinking capability with superior Critical Dimension (CD) uniformity for several years. However, NIL had been considered having difficulty to be established as mass-production technology, unless the challenge of defectivity control is overcome. The defects of NIL are classified into the non-fill defect, the template defect, and the plug defect. In order to reduce these defects, establishment of the technical infrastructures is important with the innovations of equipment, material, and template technologies. Recently, the investment to lithography becomes heavier burden for a semiconductor device maker, as lithography technology has been more difficult for further pattern shrinking. Therefore, expectation of NIL realization has emerged again. This paper describes current NIL technical status and refers to a future NIL patterning innovation such as a desktop lithography.
© (2011) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
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Tatsuhiko Higashiki, Tetsuro Nakasugi, and Ikuo Yoneda "Nanoimprint lithography for semiconductor devices and future patterning innovation", Proc. SPIE 7970, Alternative Lithographic Technologies III, 797003 (17 March 2011); https://doi.org/10.1117/12.882940
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KEYWORDS
Nanoimprint lithography
Lithography
Semiconducting wafers
Optical lithography
Extreme ultraviolet lithography
Semiconductors
Photomasks
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