Paper
28 March 2011 Litho process control via optimum metrology sampling while providing cycle time reduction and faster metrology-to-litho turn around time
K.-H. Chen, Jacky Huang, W.-T. Yang, C.-M. Ke, Y.-C. Ku, John Lin, Kaustuve Bhattacharyya, Evert Mos, Mir Shahrjerdy, Maurits van der Schaar, Steffen Meyer, Spencer Lin, Jon Wu, Sophie Peng, Albert Li, Nikki Chang, Roy Chu, Cathy Wang
Author Affiliations +
Abstract
In keeping up with the tightening overall budget in lithography, metrology requirements have reached a deep subnanometer level [1]. This drives the need for clean metrology (resolution and precision). Results have been published of a thorough investigation of a scatterometry-based platform from ASML [7], showing promising results on resolution, precision, and tool matching for overlay, CD and focus [2 - 6]. But overall requirements are so extreme that all measures must be taken in order to meet them. In light of this, in addition to above-mentioned need for resolution and precision, the speed and sophistication in communication between litho and metrology (feedback control) are also becoming increasingly crucial. An effective sampling strategy for metrology plays a big role in order to achieve this. This study discusses results from above mentioned scatterometry-based platform in light of sampling optimization. For overlay, various sampling schemes (dense / sparse combinations as well as inter and intra field schemes) were used on many production lots. The effectiveness of such sample schemes were studied to reveal an ideal sampling scheme that can result in 0.5nm to 1nm gain in overlay control (compare to today's practice). Moreover, cycle time contribution of metrology (at litho) in overall cycle time of a full process flow was investigated and quantified with the concept of integrated metrology. Results indicate a cycle time reduction per layer (if an integrated concept is used) of 3 to 5 hours, which can easily add up to several days of total cycle time reduction for a fab.
© (2011) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
K.-H. Chen, Jacky Huang, W.-T. Yang, C.-M. Ke, Y.-C. Ku, John Lin, Kaustuve Bhattacharyya, Evert Mos, Mir Shahrjerdy, Maurits van der Schaar, Steffen Meyer, Spencer Lin, Jon Wu, Sophie Peng, Albert Li, Nikki Chang, Roy Chu, and Cathy Wang "Litho process control via optimum metrology sampling while providing cycle time reduction and faster metrology-to-litho turn around time", Proc. SPIE 7971, Metrology, Inspection, and Process Control for Microlithography XXV, 797105 (28 March 2011); https://doi.org/10.1117/12.879218
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Cited by 4 scholarly publications.
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KEYWORDS
Semiconducting wafers

Metrology

Overlay metrology

Time metrology

Process control

Lithography

Tin

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