In order to ensure long-term profitability, driving the operational costs down and improving the yield of a DRAM
manufacturing process are continuous efforts. This includes optimal utilization of the capital equipment. The costs of
metrology needed to ensure yield are contributing to the overall costs. As the shrinking of device dimensions continues,
the costs of metrology are increasing because of the associated tightening of the on-product specifications requiring more
The cost-of-ownership reduction is tackled by increasing the throughput and availability of metrology systems.
However, this is not the only way to reduce metrology effort. In this paper, we discuss how the costs of metrology can
be improved by optimizing the recipes in terms of the sampling layout, thereby eliminating metrology that does not
contribute to yield.
We discuss results of sampling scheme optimization for on-product overlay control of two DRAM manufacturing
processes at Nanya Technology Corporation. For a 6x DRAM production process, we show that the reduction of
metrology waste can be as high as 27% and overlay can be improved by 36%, comparing with a baseline sampling
scheme. For a 4x DRAM process, having tighter overlay specs, a gain of ca. 0.5nm on-product overlay could be
achieved, without increasing the metrology effort relative to the original sampling plan.