20 April 2011 EUV defect characterization study on post litho and etch for 1x and 2x node processes
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Proceedings Volume 7971, Metrology, Inspection, and Process Control for Microlithography XXV; 797126 (2011); doi: 10.1117/12.881518
Event: SPIE Advanced Lithography, 2011, San Jose, California, United States
Abstract
EUV mask metrology and inspection challenges as well as EUV patterned wafer metrology and inspection strategies must be addressed to enable EUV patterning for pilot and high volume production. In this work we present a defectivity analysis of defects from post EUV lithography and etch and the correlation between them on 40nm and 28nm half pitch (HP) line/space structures. The objective of the work was to study the lithography and etch process window vs. pitch as well as to characterize the performance of a DUV brightfield wafer inspection system on EUV stacks in order to detect EUV related DOI's. In addition to defect characterization for the lithography and etch layers, we present the results of scattering simulation from these layers, with polarized 266nm DUV illumination, to provide insight on the light-pattern interaction and on the critical detection parameters.
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Ofir Montal, Man-Ping Cai, Kfir Dotan, Ido Dolev, Tom Wallow, Obert Wood, Uzo Okoroanyanwu, Moshe Rozentsvige, Chris Ngai, Chris Bencher, Amiad Conley, "EUV defect characterization study on post litho and etch for 1x and 2x node processes", Proc. SPIE 7971, Metrology, Inspection, and Process Control for Microlithography XXV, 797126 (20 April 2011); doi: 10.1117/12.881518; https://doi.org/10.1117/12.881518
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KEYWORDS
Etching

Extreme ultraviolet

Semiconducting wafers

Lithography

Deep ultraviolet

Polarization

Scattering

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