20 April 2011 Wafer-edge defect reduction for tri-layer materials in BEOL applications
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Abstract
As the semiconductor feature size continues to shrink, the thickness of photo resist needs to be thinner and thinner to prevent resist features from collapse. Coupling with the need of high NA lithography for small feature patterning, both the reflectance control and the etch budget on resist thickness are becoming major challenges for lithographers. One way to simultaneously satisfy the needs of superior low reflectance, sufficient etch resistance and minimizing the resist feature collapse is adopting tri-layer lithography scheme. The tri-layer scheme has been successfully implemented in our manufacturing flow for FEOL (Front-End-of-Line) application. This work investigated the application of tri-layer scheme to BEOL (Back-End-of-Line) AlCu patterning. One critical problem met in this application is the defect that majorly originates from wafer edge after AlCu patterning. The defects were finally ascribed to the hump formation of Si-rich hard-mask by EBR (Edge Bead Removal) process. The hump of Si-rich hard-mask yields etch masking behavior during AlCu etch accordingly leads to pattern bridging or peeling of inorganic hard-mask after AlCu patterning. To reduce the defect, several evaluations were made to suppress the hump formation, including the EBR optimization, bake condition of Si-rich hard-mask, film stacking architecture of tri-layer by EBR rinse and surfactant additive added Si-rich hard-mask. A synergy effect among process factors has been proposed to effectively fix the defect problem around wafer edge.
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J. R. Du, C. H. Huang, Elvis Yang, T. H. Yang, K. C. Chen, Chih-Yuan Lu, "Wafer-edge defect reduction for tri-layer materials in BEOL applications", Proc. SPIE 7971, Metrology, Inspection, and Process Control for Microlithography XXV, 79712L (20 April 2011); doi: 10.1117/12.879191; https://doi.org/10.1117/12.879191
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