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15 April 2011 Patterning process study for 30nm hole
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In order to continue scaling down the feature sizes of the devices until extreme ultraviolet lithography (EUVL) reaches to production capability, the alternative methods such as double patterning technology (DPT) and spacer patterning technology (SPT) are applied for half pitch (hp) 2x~3x nm line / space imaging. In the storage node of DRAM, both stable hole patterning and high dielectric constant (ε) material development are key factors to secure the capacitance. In terms of hole patterning, we anticipate that hp 4x nm hole will be possible with combination of vertical and horizontal lines. However, the patterning process for hp 3x nm hole has to find a solution in trade-off relationship between process stability, complexity and cost of ownership (CoO) until EUVL is accomplished. In this paper, we will demonstrate 3x nm hole patterning process using double patterning technology combined with negative tone development (NTD). Contrary to general method (positive tone development with dark field mask) for hole patterning, intention to use NTD with bright field mask will first be discussed. Evaluation and analysis of the simulated and experimental results will be discussed for block CD uniformity improvement. In addition to patterning, overlay performance will be tested through NXT 1950i to confirm DPT process feasibility. Finally, process integrations including etch process will be demonstrated.
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Kilyoung Lee, Cheolkyu Bok, Jaeheon Kim, Byounghoon Lee, Jongsik Bang, Hyunkyung Shim, Sungjin Kim, James Moon, Donggyu Yim, and Sung-Ki Park "Patterning process study for 30nm hole", Proc. SPIE 7972, Advances in Resist Materials and Processing Technology XXVIII, 79720P (15 April 2011);

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