Underlayers (UL), such as organic planarizing layers (OPLs) or spin-on carbon (SOC) layers, play a very important role
in various integration schemes of chip manufacturing. One function of OPLs is to fill in pre-existing patterns on the
substrate, such as previously patterned vias, to enable lithographic patterning of the next level. More importantly, OPL
resistance to reactive ion etch (RIE) processes used to etch silicon-containing materials is essential for the successful
pattern transfer from the resist into the substrate. Typically, the pattern is first transferred into the OPL through a two-step
RIE sequence, followed by the transfer into the substrate by a fluorine-containing RIE step that leaves the OPL
pattern mainly intact. However, when the line/space patterns are scaled down to line widths below 35 nm, it was found
that this last RIE step induces severe pattern deformation ("wiggling") of the OPL material, which ultimately prevents
the successful pattern transfer into the substrate.
In this work, we developed an efficient process to evaluate OPL materials with respect to their pattern transfer
performance. This allowed us to systematically study material, substrate and etch process parameters and draw
conclusions about how changes in these parameters may improve the overall pattern transfer margin.