This PDF file contains the front matter associated with SPIE Proceedings Volume 7973, including the Title Page, Copyright information, Table of Contents, Introduction, and the Conference Committee listing.

The effect of the source pixel intensity and polarization on imaging is analyzed. The pixilated source is an artifact of the discrete overlapping diffraction orders from the pupil stop of the illumination and from the pupil stop of the projection lens. The intensity of the discrete source pixels is sensitive to the image log slope (ILS) and the mask error enhancement factor (MEEF). There are trade-offs between minimizing the MEEF and maximizing the process window (PW). The pixilated source intensity allows one to better balance these trade-offs. Although the source intensity has a large effect on MEEF and PW, mixed polarization states of XY and transverse magnetic (TM) or of transverse electric (TE) and TM have limited value because of low k1 sampling of the projection lens and because effects of the wafer stack of thin-films dominate.

This paper will describe the development, qualification, monitoring, and integration into a production environment of the world's first fully programmable illuminator for optical lithography. FlexRay ^TM, a programmable illuminator based on a MEMs multi-mirror array that was developed for TWINSCAN XT:19x0i and TWINSCAN NXT series ASML immersion scanners, was first installed in January 2010 at Albany Nanotech, with subsequent tools installed in IBM's East Fishkill Manufacturing facility. After a brief overview of the concept and benefits of FlexRay, this paper will provide a comprehensive assessment of its reliability and imaging performance. A CD-based pupil qualification (CDPQ) procedure will be introduced and shown to be an efficient and effective way to monitor pupil performance. Various CDPQ and in-resist measurement results will be described, offering convincing evidence that FlexRay reliably generates high-quality pupils and is well suited for high volume manufacturing at lithography's leading edge.

Joint optimization (JO) of source and mask together is known to produce better SMO solutions than sequential optimization of the source and the mask. However, large scale JO problems are very difficult to solve because the global impact of the source variables causes an enormous number of mask variables to be coupled together. This work presents innovation that minimize this runtime bottleneck. The proposed SMO parallelization algorithm allows separate mask regions to be processed efficiently across multiple CPUs in a high performance computing (HPC) environment, despite the fact that a truly joint optimization is being carried out with source variables that interact across the entire mask. Building on this engine a progressive deletion (PD) method was developed that can directly compute "binding constructs" for the optimization, i.e. our method can essentially determine the particular feature content which limits the process window attainable by the optimum source. This method allows us to minimize the uncertainty inherent to different clustering/ranking methods in seeking an overall optimum source that results from the use of heuristic metrics. An objective benchmarking of the effectiveness of different pattern sampling methods was performed during postoptimization analysis. The PD serves as a golden standard for us to develop optimum pattern clustering/ranking algorithms. With this work, it is shown that it is not necessary to exhaustively optimize the entire mask together with the source in order to identify these binding clips. If the number of clips to be optimized exceeds the practical limit of the parallel SMO engine one can starts with a pattern selection step to achieve high clip count compression before SMO. With this LSSO capability one can address the challenging problem of layout-specific design, or improve the technology source as cell layouts and sample layouts replace lithography test structures in the development cycle.

Source Mask Optimization (SMO) is one of the most important techniques available for extending ArF immersion lithography¹. However, imaging with a small k1² factor (~0.3 or smaller) is very sensitive to errors in the illumination pupil². As a result, care must be taken to insure that the source solution from SMO can be produced by the real illuminator, which is subject to its own imaging constraints. One approach is to include an illuminator simulator in the SMO loop so that only realizable illumination pupils are considered during optimization. Furthermore, any illumination pupil predictor used in SMO should operate quickly compared to the imaging simulation if it is to avoid increasing the computational load.

A cost-efficient technique for full-chip source and mask optimization is proposed in this paper. This technique has two components: SMO source optimization for full-chip and flexible mask optimization (FMO). During the technology development stage of source optimization, a novel pattern-selection technique was used to identify critical clips from a full-set of design clips; SMO was then used to optimize the source based on those selected critical-clips. This pattern-selection technique enables reasonable SMO runtime to optimize the source that covers the full range of patterns. During the process development stage and product tapeout stage, FMO is employed. The FMO framework allows the use of different OPC computational techniques on different chip areas that have different sensitivities to process variations. Advanced OPC methods are applied only where they are needed, therefore achieving optimum process performance with the least tapeout and mask cost.

This paper reports on a simulation study in which we compare different possibilities to find a litho solution for SRAM and Logic for planar technology nodes between 28 nm and 20 nm, using 193 nm immersion lithography. At these nodes, it becomes essential to include the layout itself into the optimization process. The so-called gridded layout style is an attractive candidate to facilitate the printability of several layers, but the benefit of this style, as compared to less restricted layout styles, is not well quantified for the various technology nodes of interest. We therefore compare it with two other, less restricted, layout styles, on an identical (small) SRAM-Logic test chip. Exploring a number of paths in the layout-style - litho-options search space, we try to quantify merits and trade-offs for some of the relevant options. We will show that layout restrictions are really becoming mandatory for the technology nodes studied in this paper. Other important enablers for these aggressive nodes are multiple patterning, the use of a local-interconnect layer, negative-tone development, SMO and the use of optimized free-form illumination sources (from which we also include a few initial wafer results).

Source-mask optimization (SMO) in optical lithography has in recent years been the subject of increased exploration as an enabler of 22/20nm and beyond technology nodes [1-6]. It has been shown that intensive optimization of the fundamental degrees of freedom in the optical system allows for the creation of non-intuitive solutions in both the source and mask, which yields improved lithographic performance. This paper will demonstrate the value of SMO software in resolution enhancement techniques (RETs). Major benefits of SMO include improved through-pitch performance, the possibility of avoiding double exposure, and superior performance on two dimensional (2D) features. The benefits from only optimized source, only optimized mask, and both source and mask optimized together will be demonstrated. Furthermore, we leverage the benefits from intensively optimized masks to solve large array problems in memory use models (MUMs). Mask synthesis and data prep flows were developed to incorporate the usage of SMO, including both RETs and MUMs, in several critical layers during 22/20nm technology node development. Experimental assessment will be presented to demonstrate the benefits achieved by using SMO during 22/20nm node development.

A method to resolve 20nm node of SRAM contact layer whose minimum pitch is 90nm with enough process latitude is shown. To achieve the target by single exposure under condition of ArF and 1.35 of NA a way to optimize lithography parameters and layout parameters simultaneously is applied that is called co-optimization. At first the memory cell is optimized from several viewpoints of device and lithography, and then the entire memory cell block including the array circuit is optimized. It proves that combination of co-optimization and insertion of SRAF works very well considering the appropriate printed shape required by the device layout. The co-optimization is compared to such a conventional method as OPC. The performance is better than conventional OPC. Especially the MEFF is much better and the evaluation to find the mechanism is shown. It proves that complex patterns with many fragments make MEEF higher. The superior characteristics of co-optimization are analyzed by the result of Linear Programming that can find the strict solution. The pixel source shape has become almost same as one by co-optimization. The solution is achieved by binary mask with simple patterns and the simple source shape. It is crucial for COO.

Double exposure techniques are an economically viable method for extending the life of the current 193nm wavelength immersion lithography techniques into future generations of semiconductor scaling. One popular example of double exposure is the use of double dipole illumination, where the X and Y dipoles are separately optimized for vertical and horizontal features respectively. The primary challenge in such double exposure techniques lies in the process of target layout decomposition into patterns that can be optimally printed using their respective source. Current approaches for decomposition are rule-based. They suffer from the drawbacks of scalability, rule count explosion and inability to guarantee sufficient yield in the presence of process variation. Further, rules are characterized specific to sources and are relatively easy to develop for dipoles, but far more difficult to develop for more complex sources such as used in source mask optimization (SMO). Decomposed target layouts have to further undergo optical proximity correction (OPC) in order to be converted to a mask for use in manufacturing. In this paper, we propose a novel approach which integrates the processes of decomposition and optical proximity correction. We preclude the intermediate target decomposition stage. Instead, we directly optimize the masks for both exposures simultaneously in order to obtain a wafer image that both closely matches the target layout and is also robust to process variation. For this purpose, we define a lithographic cost function that is a weighted sum of intensity error and intensity slope. We develop methods to analytically predict the change in this cost function due to movement of fragments on each mask. We then utilize a gradient-descent algorithm for fragment movement to minimize the cost function. Since our methodology is based on the knowledge of the SOCS decomposition kernels, it is not restricted to dipoles alone, but can be utilized for any complex sources for which such kernels are known. Our experiments on 1x metal (M1) show significant improvement in layout process window compared to traditional rule-based decomposition methods.

As reported previously, the IBM Alliance has established a DETO (Double-Expose-Track-Optimized) baseline, in collaboration with ASML, TEL, and CNSE, to evaluate commercially available DETO photoresist system for the manufacturing of advanced logic devices. Although EUV lithography is the baseline strategy for <2x nm logic nodes, alternative techniques are still being pursued. The DETO technique produces pitch-split patterns capable of supporting 16 nm and 11 nm node semiconductor devices. We present the long-term monitoring performances of CD uniformity (CDU), overlay, and defectivity of our DETO process. CDU and overlay performances for controlled experiments are also presented. Two alignment schemes in DETO are compared experimentally for their effects on inter-level & intralevel overlays, and space CDU. We also experimented with methods for improving CDU, in which the CD-Optimizer^TMand DoseMapper^TM were evaluated separately and in tandem. Overlay improvements using the Correction Per Exposure (CPE) and the intra-field High-Order Process Correction (i-HOPC) were compared against the usual linear correction method. The effects of the exposure field size are also compared between a small field and the full field. Included in all the above, we also compare the performances derived from stack-integrated wafers and bare-Si wafers.

We successfully demonstrate a new approach to achieve 15nm half pitch with a spacer based selfaligned triple patterning (SATP). This new concept has a single spacer deposition and etch step to achieve 15nm half pitch using immersion lithography. Current spacer based triple or quadruple patterning approaches use two iterations of "spacer deposition / spacer etch" for pitch splitting, thus generating multi-modal trench CD, line CD and, trench depth population leading to challenging process control. The new concept overcomes CD population issues and reduces additional steps over implemented double patterning, thus could relax process window. The key innovative aspect is an undercut dry trim achieved by a selective dry etch process, followed by a flowable CVD (Eterna^TM FCVD^TM) based gap-fill that can fill the undercut structures.

Double patterning technology (DPT) provides the extension to immersion lithography before EUV lithography or other alternative lithography technologies are ready for manufacturing. Besides the additional cost due to DPT processes over traditional single patterning process, DPT design restrictions are of concerns for potential additional design costs. This paper analyzes design restrictions introduced by DPT in the form of DPT restricted design rules, which are the interface between design and technology. Both double patterning approaches, Litho-Etch-Litho-Etch (LELE) and Self-Aligned Double Patterning with spacer lithography (SADP), are studied. DPT design rules are summarized based on drawn design layers instead of decomposed layers. It is shown that designs can be made DPT compliant designs if DPT design rules are enforced and DPT coloring check finds no odd cycles. This paper also analyzes DPT design rules in the design rule optimization flow with examples. It is essential to consider DPT design rules in the integrated optimization flow. Only joint optimization in design rules between design, decomposition and process constraints can achieve the best scaled designs for manufacturing. This paper also discusses DPT enablement in the design flow where DPT aware design tools are needed so that final designs can meet all DPT restricted design rules.

Double patterning with Spacer (DPS) is now widely accepted as a viable technology for the further extension of 193nm lithography towards the 22nm /18nm technology nodes. DPS was primary introduced for the manufacturing of flash memory due to its 1D design geometry. However, DPS is now becoming a main stream technology for advanced technology nodes for logic product. DPS results in alignment and overlay marks with reduced image contrast after completion of spacer patterning. Consequently there is an elevated risk that the overlay performance of the cut lithography layer on the spacer [1] may be negatively impacted. Initial studies indicate that it may be necessary to consider new mark designs. In this paper, we discuss the basic design of the Nikon alignment marks and make a statistical assessment of their relative performance. The self aligned spacer process results in asymmetric spacers. That are two types of surface (inside and outside) of the spacer are formed. The impact of this asymmetry is also being assessed. Mark geometries are characterized with 3D-AFM measurement and alignment / overlay performance analysis.

Self-aligned double patterning (SADP) lithography is a novel lithography technology that has the intrinsic capability to reduce the overlay in the double patterning lithography (DPL). Although SADP is the critical technology to solve the lithography difficulties in sub-32nm 2D design, the questions - how to decompose a layout with reasonable overlay and how to perform a decomposability check - are still two open problems with no published work. In this paper, by formulating the problem into a SAT formation, we can answer the above two questions optimally. This is the first published paper with detailed algorithm to perform the SADP decomposition. In a layout, we can efficiently check whether a layout is decomposable. For a decomposable layout, our algorithm guarantees to find a decomposition solution with reasonable overlay reduction requirement. With little changes on the clauses in the SAT formula, we can address the decomposition problem for both the positive tone process and the negative tone process. Experimental results validate our method, and decomposition results for Nangate Open Cell Library and larger test cases are also provided with competitive run times.

In many ways, sidewall spacer double patterning has created a new paradigm for lithographic roadmaps. Instead of using lithography as the principal process for generating device features, the role of lithography becomes to generate a mandrel (a pre-pattern) off-of-which one will subsequently replicate patterns with various degrees of density multiplication. Under this new paradigm, the innovativeness of various density multiplication techniques is as critical to the scaling roadmap as the exposure tools themselves. Sidewall spacer double patterning was the first incarnation of mandrel based patterning; adopted quickly in NAND flash where layouts were simple and design space was focused. But today, the use of advanced automated decomposition tools are showing spacer based patterning solutions for very complex logic designs. Future incarnations can involve the use of laminated spacers to create quadruple patterning or by retaining the original mandrel as a method to obtain triple patterning. Directed self-assembly is yet another emerging embodiment of mandrel based patterning, where selfseparating polymers are registered and guided by the physical constraint of a mandrel or by chemical pre-pattern trails formed onto the substrate. In this summary of several bodies of work, we will review several wafer level demonstrations, all of which use various forms of mandrel or stencil based density multiplication including sidewall spacer based double, triple and quadruple patterning techniques for lines, SADP for via multiplication, and some directed self-assembly results all capable of addressing 15nm technology node requirements and below. To address concerns surrounding spacer double patterning design restrictions, we show collaboration results with an EDA partner to demonstrate SADP capability for BEOL routing layers. To show the ultimate realization of SADP, we partner with IMEC on multiple demonstrations of EUV+SADP.

In this work, a physical model is constructed to describe a thermal cure double patterning photoresist process. The basic lithographic response of each photoresist can be accurately described using the conventional chemically amplified resist modeling approach. Experimental data reveals that although the thermal cure process removes all detectable photosensitivity from the imaged first resist, it does increase the materials solubility in the second resist development process. It is theorized that this solubility change results from thermal de-protection of the resist polymer during the cure. Introduction of a first-order thermal de-protection process to the model, results in simulations that match the experimental data. Measurement of actinic optical properties show that the first resist remains optically stable during its processing (in the regions remaining on the wafer after development) but that the BARC material undergoes significant optical changes in open areas where the first resist has been removed. The calibrated process model is tested against experimental data generated under other optical conditions; good quantitative and qualitative agreement is observed and in one case the simulation results suggest a plausible mechanism for observed process failure.

To print sub 22nm node features, current lithography technology faces some tool limitations. One possible solution to overcome these problems is to use the double patterning technique (DPT). The principle of the double patterning technique is pitch splitting where two adjacent features must be assigned opposite masks (colors) corresponding to different exposures if their pitch is less than a predefined minimum coloring pitch. However, certain design orientations for which pattern features separated by more than the minimum coloring pitch cannot be imaged with either of the two exposures. In these directions, the contrast and the process window are degraded because constructive interferences between diffractive orders in the pupil plane are not sufficient. The 22nm and 16nm nodes require the use of very coherent sources that will be generated using SMO (source mask cooptimization). Such pixelized sources while helpful in improving the contrast for selected configurations, can lead to degrade it for configurations which have not been counted for during the SMO process. Therefore, we analyze the diffractive orders interactions in the pupil plane in order to detect these limited orientations in the design and thus propose a new double patterning decomposition algorithm to enlarge the process window and the contrast of each mask.

Spacer-defined double patterning was investigated as a patterning option for 20/14-nm logic technology's back-end-of-line (BEOL), and compared with the double patterning options of front-end-of-line (FEOL). Negative spacer-defined double patterning was used to provide less overlay impact and variable CD control on the metal lines compared with other double patterning techniques. Block lithography as a 2nd exposure was able to maintain better tip-to-tip and tip-to-line fidelity by forming lines that behave as a additive etch block. SiO₂ spacer was directly deposited on resist core-mandrel via a low-temperature deposition process. Resist integrity was optimized through aerial image and mask optimization as well as resist selection processes. Design decomposition of the BEOL layout was identified as a major challenge in enabling the spacer-defined double patterning. Finally, successful integration of the patterning into the BEOL device was demonstrated.

Different mask models have been compared: rigorous electromagnetic field (EMF) modeling, rigorous EMF modeling with decomposition techniques and the thin mask approach (Kirchhoff approach) to simulate optical diffraction from different mask patterns in projection systems for lithography. In addition, each rigorous model was tested for two different formulations for partially coherent imaging: The Hopkins assumption and rigorous simulation of mask diffraction orders for multiple illumination angles. The aim of this work is to closely approximate results of the rigorous EMF method by the thin mask model enhanced with pupil filtering techniques. The validity of this approach for different feature sizes, shapes and illumination conditions is investigated.

We present a comprehensive study of applicability of a fast 3D mask model in the context of source-mask optimization to advanced nodes. We compare the results of source optimization (SO) and source-mask optimization (SMO) with and without incorporating a fast 3D mask model to the rigorous 3D mask simulations and wafer data at 22 nm technology node. We do this comparison in terms of process metrics such as depth of focus (DOF), exposure latitude (EL), and mask error enhancement factor (MEEF). We try to answer the question of how much the illumination shape changes with the introduction of mask topography effect. We also investigate if the illumination change introduces any mask complexity and at which level. Correlation between MEEF and any mask complexity due to source variation is also explored. We validate our simulation predictions with experimental data.

FlexRay programmable illumination and LithoTuner software is combined in several use cases. The first use case is optical proximity error (OPE) minimization. Simulation predicts the rms OPE error is reduced by 39% with LithoTuner and FlexRay, and is confirmed via experiment with a reduction of 33%. For minimizing the OPE error, two types of illumination tuning was performed, sigma tuning and freeform tuning. The sigma tuning is able to reduce the mean-totarget critical dimension (CD) error, but the CD error variance is unaffected. Freeform tuning, however, is able to reduce both the mean-to-target CD and the CD error variance. The second use case is matching two ArF scanners, a XT:1950Hi with FlexRay to a XT:1700Fi with diffractive optical element (DOE) illumination. With LithoTuner and FlexRay, simulation predicts the CD error post-matching is reduced by 51%, and experiment was able to achieve a reduction of 29%.

Once a process is set-up in an integrated circuit (IC) manufacturer's fabrication environment, any drift in the proximity fingerprint of the cluster will negatively impact the yield. In complement to the dose, focus and overlay control of the cluster, it is therefore also of ever growing importance to monitor and maintain the proximity stability (or CD through pitch behavior) of each cluster. In this paper, we report on an experimental proximity stability study of an ASML XT:1900i cluster for a 32 nm poly process from four different angles. First, we demonstrate the proximity stability over time by weekly wafer exposure and CD through pitch measurements. Second, we investigate proximity stability from tool-to-tool. In a third approach, the stability over the exposure field (intra-field through-pitch CD uniformity) is investigated. Finally, we verify that proximity is maintained through the lot when applying lens heating correction. Monitoring and maintaining the scanner's optical proximity through time, through the lot, over the field, and from toolto- tool, involves extensive CD metrology through pitch. In this work, we demonstrate that fast and precise CD through pitch data acquisition can be obtained by scatterometry (ASML YieldStar^TM S-100), which significantly reduces the metrology load. The results of this study not only demonstrate the excellent optical proximity stability on a XT:1900i exposure cluster for a 32 nm poly process, but also show how scatterometry enables thorough optical proximity control in a fabrication environment.

Scanner mismatch has become one of the critical issues in high volume memory production. There are several components that contribute to the scanner CD mismatch. One of the major components is illumination pupil difference between scanners. Because of acceleration of dimensional shrinking in memory devices, the CD mismatch became more critical in electrical performance and process window. In this work, we demonstrated computational lithography model based scanner matching for sub 3x nm memory devices. We used ASML XT:1900Gi as a reference scanner and ASML NXT:1950i as the to-be-matched scanner. Wafer metrology data and scanner specific parameters are used to build a computational model, and determine the optimal settings by model simulation to minimize the CD difference between scanners. Nano Geometry Research (NGR) was used as a wafer CD metrology tool for both model calibration and matching result verification. The extracted pupil parameters from measured source map from both before and after matching are inspected and analyzed. Simulated and measured process window changes by applying the matching sub-recipe are also evaluated.

The 22-nm technology node presents a real breakthrough compared to previous nodes in the way that state of the art scanner will be limited to a numerical aperture of 1.35. Thus we cannot "simply" apply a shrink factor from the previous node, and tradeoffs have to be found between Design Rules, Process integration and RET solutions in order to maintain the 50% density gain imposed by the Moore's law. One of the most challenging parts to enable the node is the ability to pattern Back-End Holes and Metal layers with sufficient process window. It is clearly established that early process for these layers will be performed by double patterning technique coupled with advanced OPC solutions. In this paper we propose a cross comparison between possible double patterning solutions: Pitch Splitting (PS) and Sidewall Image Transfer (SIT) and their implication on design rules and CD Uniformity. Advanced OPC solutions such as Model Based SRAF and Source Mask Optimization will also be investigated in order to ensure good process control. This work is a part of the Solid's JDP between ST, ASML and Brion in the framework of Nano2012 sponsored by the French government.

ArF immersion lithography will be the main candidate for lithography patterning at the 22nm node. For both logic and memory type applications, double patterning techniques have to be applied to reach design pitches well below 70nm. In the lithography this combines aggressive imaging at low k₁ (0.28... 0.31) and aggressive absolute CDU requirements (approximately 6-10% of nominal CD) of 1.5..2nm 3σ. We will look into the lithography requirements to achieve such aggressive CDU numbers and will discuss solutions for achieving the required level of intra-field, inter-field, waferto- wafer and scanner-to-scanner CD variations

The desire to reduce cost in volume manufacturing has driven up the throughput in the lithographic exposure machines. As a result the power transmitted in the projection optics increases. Although small, the absorption levels in the lens materials are not zero, which leads to localized heating of the lens and hence lens aberrations. To squeeze out the maximum process windows, the pupil shapes have transformed from simple annular shapes to shapes with very concentrated poles. As a result, the exposure energy transported through the lens is no longer equally distributed over the lenses of the projection options. Instead only a fraction of the lens gets to transport the total power. This concentration of power further aggravates the lens heating induced aberrations and enhances the importance of advanced lens heating control schemes which are available on ASML scanners. To analyze the effects of lens heating on the final imaging, a model was developed by the lens manufacturer Carl Zeiss SMT GmbH, and incorporated into a litho simulation environment by ASML BRION. This tool can be used to analyze the impact of dose/throughput, illumination shapes and reticle layout on aberrations. It provides a means to assess potential lens heating issues even before production masks are manufactured. Moreover, this computational tool opens the possibility to calculate parameters for lens heating correction, rather than measuring them, saving valuable machine time. In this paper, the performance of the novel computational lens heating control is demonstrated on wafer and compared with the traditional way of measuring the relevant parameters. In addition, a modeling study is performed to assess possible lens heating effects for freeform or non-traditional source shapes, thereby demonstrating the advanced correction potential of ASML latest aberration manipulator, called FlexWave^TM.

In order to realize further improvement of productivity of semiconductor manufacturing, higher throughput and better imaging performance are required for the exposure tool. Therefore, aberration control of the projection lens is becoming more and more important not only for cool status performance but also heating status. In this paper, we show the improvements of cool status lens aberration, including scalar wavefront performance and polarization aberration performance. We also discuss various techniques for controlling thermal aberrations including reduction of heat in the lens, simulation, compensating knob, and adjusting method with actual imaging performance data during heating and cooling.

In this paper, we discuss the accuracy of resist model calibration under various aspects. The study is done based on an extensive OPC dataset including hundreds of CD values obtained with immersion lithography for the sub-30 nm node. We address imaging aspects such as the role of Jones matrices, laser bandwidth and mask bias. Besides we focus on the investigation on metrology effects arising from SEM charging and uncertainty between SEM image and feature topography. For theses individual contributions we perform a series of resist model calibrations to determine their importance in terms of relative RMSE (Root Mean Square Error) and it is found that for the sub-30 nm node they all are not negligible for accurate resist model calibration.

To achieve the 2 nm overlay accuracy required for double patterning, we have introduced the NSR-S620D immersion scanner that employs an encoder metrology system. The key challenges for an encoder metrology system include its stability as well as the methods of calibration. The S620D has a hybrid metrology system consisting of encoders and interferometers, in XY and Z. The advantage of a hybrid metrology system is that we can continuously monitor the position of the stage using both encoders and interferometers for optimal positioning control, without any additional metrology requirements or throughput loss. To support this technology, the S620D has various encoder calibration functions that make and maintain the ideal grid, and control focus. In this paper we will introduce some of the encoder calibration functions based on the interferometer. We also provide the latest performance of the tool, with an emphasis on overlay and focus control, validating that the NSR-S620D delivers the necessary levels of accuracy and stability for the production phase of double patterning.

ArF water immersion lithography is expected to be used down to the 22nm hp node or below. However, such advancements in technology nodes have led to extremely small process margins. This necessitates more accurate means of process control. CD uniformity of the photo-resist (PR) image is affected by many sources. In the case of the exposure tool-CD error on the reticle, as well as exposure dose and focus errors are the key factors. For the PR process, heterogeneity of the stacked PR film thickness, post exposure bake (PEB) plate temperature, and development have an impact. Further, the process wafer also has error sources that include under-layer uniformity and wafer flatness. Fortunately, the majority of these factors is quite stable in a volume production process and can be compensated for by adjusting exposure dose and focus in the scanner. A technique to calculate exposure dose and focus correction values simultaneously from the measured PR image feature was reported previously [1]. In addition, a demonstration of a correction loop using a neural network calculation model was reported in SPIE 2010 [2], and the corrected CD uniformity was less than 1.5 nm (3-sigma) within the wafer. In this paper, we will report the latest CD uniformity correction results achieved with the NSR-S620D ArF immersion scanner using correction values estimated by scatterometry and CD-SEM. The method of correction using CD-SEM is newly developed. A maximum of nine parameters extracted from the PR profile are used in this correction. In general, the CD variation of an isolated line pattern caused by focus error is more sensitive than that of a dense pattern. Thus, we estimate the focus error from the isolated pattern, with the dose error estimated using both isolated and dense patterns. The Nikon CDU Master then derives the optimal control parameters for each compensation function in the scanner using the exposure dose and focus correction data, and the NSR-S620D is able to control higher order dose and focus distribution. This advanced level of control capabilities enables precise correction of the complicated CD error distribution that is caused by heterogeneities in the process.

As leading edge lithography moves to 22-nm design rules, low k1 technologies like double patterning are the new resolution enablers, and system control and setup are the new drivers to meet remarkably tight process requirements. The way of thinking and executing setup and control of lithography scanners is changing in four ways. First, unusually tight process tolerances call for very dense sampling [1], which in effect means measurements at high throughput combined with high order modeling and corrections to compensate for wafer spatial fingerprint. Second, complex interactions between scanner and process no longer allow separation of error sources through traditional metrology approaches, which are based on using one set of metrology tools and methods for setup and another for scanner performance control. Moreover, setup and control of overlay is done independently from CD uniformity, which in effect leads to independent and conflicting adjustments for the scanner. Third, traditional CD setup and control is based on the focus and dose calculated from their CD response and not from measurement of their effect on pattern profile, which allows a clean and orthogonal de-convolution of focus and dose variations across the wafer. Fourth, scanner setup and control has to take into consideration the final goal of lithography, which is the accurate printing of a complex pattern describing a real device layout. To this end we introduce a new setup and control metrology step: measuring-to-match scanner 1D and 2D proximity. In this paper we will describe the strategy for setup and control of overlay, focus, CD and proximity based on the YieldStar^TM metrology tool and present the resulting performance. YieldStar-200 is a new, high throughput metrology tool based on a high numerical aperture scatterometer concept. The tool can be used stand-alone as well as integrated in a processing track. It is suitable for determining process offsets in X,Y and Z directions through Overlay and Focus measurements respectively. In addition CD profile information can be measured enabling proximity matching applications. By using a technique [2][3][4] to de-convolve dose and focus based on the profile measurement of a well-characterized process monitor target, we show that the dose and focus signature of a high NA 193nm immersion scanner can be effectively measured and corrected. A similar approach was also taken to address overlay errors using the diffraction based overlay capability [5] of the same metrology tool. We demonstrate the advantage of having a single metrology tool solution, which enables us to reduce dose, focus and overlay variability to their minimum non-correctable signatures. This technique makes use of the high accuracy and repeatability of the YieldStar tool and provides a common reference of scanner setup and user process. Using ASML's YieldStar in combination with ASML scanners, and control solutions allows for a direct link from the metrology tool to the system settings, ensuring that the appropriate system settings can be easily and directly updated.

The 2009 ITRS update specifies wafer overlay control as one of the major tasks for the sub 40 nm nodes. Wafer overlay is strongly dependent on mask image placement error (registration errors or Reg errors)¹ in addition to CD control and defect control. The specs for registration or mask placement accuracy are twice as difficult in some of the double patterning techniques (DPT). This puts a heavy challenge on mask manufacturers (mask shops) to comply with advanced node registration specifications. Registration test masks as well as production masks were measured on a standard registration tool and the registration error was calculated and plotted. A specially developed algorithm was used to compute a correction lateral strain field that would minimize the registration error. A laser based prototype RegC^TM tool was used to generate a strain field which corrected for the pre measured registration errors. Finally the post registration error map was measured. The resulting residual registration error field with and without scale and orthogonal errors removed was calculated. In this paper we present first results of registration control experiments using the prototype RegC^TM tool.

Achieving 20nm designs with 193nm lithography is difficult even with immersion technology. At 20nm, the metal-1 pitch will be ~64nm, which is well below the 80nm limit for single exposure. In this work we extend on our earlier results [1-4] to show simulation-based patterning of both SRAMs and logic cells. This is consistent with the emerging industry consensus that regular designs and multiple exposure techniques will extend 193nm immersion as far down as 7nm [5]. The approach relies on 1D Gridded Design Rules with Lines/Cuts (1D GDR LC) selective double patterning. Due to the highly regular patterns of 1D GDR LC we are able to determine a sharp lithographic optimum as a result of numerical co-optimization of key layout parameters and lithography settings such as scanner illumination, etc. including realistic scanner capability. Critical layers (holes/cuts in 1D GDR LC) consist of a number of identical hole/cut patterns with varying density. We propose a novel algorithm for full-chip proximity correction of such critical layers. The algorithm consists of 1) a source-mask optimization step (SMO) to choose optimal scanner settings for a class of designs using standard cells, followed by 2) a final correction step applied to the entire layout to determine individual sizing for each cut to componsate for its optical/process environment. This procedure converges rapidly in our test cases producing close to 0nm CD error for each cut. Several test designs including one with approximately 100k transistors using ~20 cells from a standard cell library including both SRAM and logic cells were used, with good convergence obtained in all cases. Out procedure is a combination of an SMO step followed by cuts-OPC, the equivalent to OPC applied to cuts of 1D GDR LC designs. The procedure scales linearly with layout area and can be efficiently applied to full-chip designs.

The ability to incorporate the effect of patterned underlayers in a 3-dimensional physical resist model that truly mimics the process on real wafers could be used to formulate robust ground rules for design. We have shown as an example block level simulations, where the resist critical dimension is determined by the presence of STI (shallow trench isolation) and/or patterned gate level underneath & their relative spacing, as confirmed on wafer. We will demonstrate how the results of such study could be used for creating ground rules which are truly dependent on the interaction between the current layer resist & the patterned layers underneath. We have also developed a new way to visualize lithographic process variations in 3-D space that is useful for simulation analysis that can prove very helpful in ground rule development and process optimization. Such visualization capability in the dataprep flow to flag issues or dispose critical structures increases speed and efficiency in the mask tapeout process.

Strong resolution enhancement technologies (RETs) combined with hyper-NA ArF immersion lithography with source and mask optimization (SMO) have become necessary to achieve sufficient resolution in 2Xnm node devices. Conventional SMO methods have focused on minimizing the edge placement error and/or the cost functions of dose, focus, and mask errors. This has not, however, resolved the conflict between line and gap patterns on logic gate layouts. One issue remaining in particular is the mask error enhancement factor (MEEF). Furthermore, the pattern shapes at the line end gaps of SRAM gates remain a major challenge for logic device manufacturers. To overcome these problems, we explain the importance of controlling the light intensity profiles at line end gaps, focusing on a Panasonic product called "Mask Enhancer" that comprises an attenuated mask with a phase shifting aperture and enables light intensity profiles to be controlled easily. We demonstrate the product's effectiveness in printing gates with optimized illumination source shapes. A simulation experiment and a feasibility study confirmed that Mask Enhancer can improve the MEEF and pattern shapes at the line ends of SRAM gates.

A new method capable of fast and accurate computation of mask topography effect was described and evaluated using a broad range of test structures. Results are presented for 1D and 2D test structures as well as for advanced OPC masks such as the one generated by inverse lithography or source-mask optimization software tools. The 1D test structures is a line and space test pattern with line width of 40nm, 60nm, 80nm, 100nm, 120nm the space width varying from 40nm to 1000nm. The RMS of the difference between the model and rigorous simulations is 3.6E-3 for 27,420 points correspond to all the combinations of line widths and space widths. The standard deviation of the CD difference between the model and the rigorous calculation, calculated for 5 thresholds (0.1, 0.11, 0.12, 0.13, and 0.14) and for all the structures, is 0.48nm. For a simple 2D test pattern, the mask fields are computed using rigorous calculation and compared to the model. The difference between the fields is within the error of the rigorous calculation. The resulting wafer images are almost identical with no re-scaling of the data was applied to either the mask fields or the wafer images. To study the applicability of the model to more complex patterns we have converted a contact level layout into an inverse mask and the new mask model was applied to the data in order to simulate the wafer image.

A qualitatively new method applicable for process variability band (PVband) improvement and printability enhancement in resolution enhancement technique (RET) applications is reported. The method does not use costly simulations through the process window (PW). Instead, it utilizes a unique feedback mechanism derived from the intensity distribution information available during nominal optical proximity correction (OPC) simulation. Consequently, this Intensity Slope Correction (ISC) method provides superior performance as compared to traditional process window aware OPC tools. Preliminary results are presented. They suggest that this method can successfully be applied for improvement of integral PVband throughout the entire layout leading to global printability optimization.

As 193 nm immersion lithography is extended indefinitely to sustain technology roadmaps, there is increasing pressure to contain escalating lithography costs by identifying patterning solutions that can minimize the use of multiple-pass processes. Contact patterning for the 32/28 nm technology nodes has been greatly facilitated by just-in-time introduction of new process enablers that allow the simultaneous support of flexible foundry-oriented ground rules alongside highperformance technology, while also migrating to a single-pass patterning process. The incorporation of device based performance metrics along with rigorous patterning and structural variability studies were critical in the evaluation of material innovation for improved resolution and CD shrink along with novel data preparation flows utilizing aggressive strategies for SRAF insertion and retargeting.

A new technique is introduced to replace DOEs that are used for illumination in lithographic projectors with polarization computer generated holograms (PCGHs) that produce both arbitrary intensity and arbitrary polarization state in the illumination pupil. The additional capability of arbitrary polarization state adds an additional degree of freedom for source-mask optimization. The PCGHs are similar in design and construction to DOEs, but they incorporate polarizationsensitive elements. Three experiments are described that demonstrate different configurations of PCGHs deigned to produce a tangentially polarized ring. Measurements of ratio of polarization and polarization orientation indicate that all three configurations performed well. Experimetns are performed with visible (λ = 632.8nm) light.

As semiconductor lithography is pushed to smaller dimensions, the process yields tend to suffer due to subwavelength imaging effects. In response, resolution enhancement technologies have been employed together with optimization techniques, specifically source mask optimization (SMO), which finely tunes the process by simultaneously optimizing the source shape and mask features. However, SMO has a limitation in that it fails to compensate for undesired phase effects. For mask features on the order of the wavelength, the topography of the mask can induce aberrations which bring asymmetry to the focus-exposure matrix (FEM) and ultimately decrease the process window. This paper examines the dependency of FEM asymmetry on factors such as the illumination coherency and lens induced spherical aberration. It is shown that lens induced primary spherical aberration strongly impacts the symmetry of the FEM. In this work, phase correction is achieved by incorporating the pupil plane in an optimization. It is shown that primary spherical aberration can correct for effects including the degraded depth of focus and the tilt in the FEM for a dual trench mask. A pupil function with an optimized coefficient of primary spherical aberration balances the spherical aberration induced by the mask topography.

It is well known in the industry that the technology nodes from 30nm and below will require model based SRAF / OPC for critical layers to meet production required process windows. Since the seminal paper by Saleh and Sayegh[1][2] thirty years ago, the idea of using inverse methods to solve mask layout problems has been receiving increasing attention as design sizes have been steadily shrinking. ILT in its present form represents an attempt to construct the inverse solution to a constrained problem where the constraints are all possible phenomena which can be simulated, including: DOF, sidelobes, MRC, MEEF, EL, shot-count, and other effects. Given current manufacturing constraints and process window requirements, inverse solutions must use all possible degrees of freedom to synthesize a mask. Various forms of inverse solutions differ greatly with respect to lithographic performance and mask complexity. Factors responsible for their differences include composition of the cost function that is minimized, constraints applied during optimization to ensure MRC compliance and limit complexity, and the data structure used to represent mask patterns. In this paper we describe the level set method to represent mask patterns, which allows the necessary degrees of freedom for required lithographic performance, and show how to derive Manhattan mask patterns from it, which can be manufactured with controllable complexity and limited shot-counts. We will demonstrate how full chip ILT masks can control e-beam write-time to the level comparable to traditional OPC masks, providing a solution with maximized lithographic performance and manageable cost of ownership that is vital to sub-30nm node IC manufacturing.

Source and Mask co-Optimization (SMO) plays an increasingly important role in the advanced RETs required to continue shrinking designs in the low-k1 lithography regime. Instead of costly double pattering patterning techniques, SMO has been explored as an enabling technology for low-k1 design node. It is clear that intensive optimization of the fundamental degrees of freedom in the optical system allows for the creation of non-intuitive solutions in both the mask and the source, which leads to improved lithographic performance. In this work, source and mask shape for logic device have been optimized in order to improve process window of critical layouts which include complex 2D shape and dense contact. Tachyon SMO solution developed by BRION was introduced to obtain the optimization. In order to improve the accuracy of SMO model, AI blur which represents resist effect on wafer was considered during optimization. Based on simulation results, improvement in terms of process window as well as Mask Error Enhancement Factor (MEEF) was approximately 20 % in comparison with reference conditions. However, the corresponding experimental results should be investigated as the evidence of the performance SMO. These results demonstrate the importance of these considerations during optimization in achieving the best possible SMO results which can be applied successfully to the targeted lithography process.

At SPIE2010, excellent performance of the cutting edge immersion lithography scanner, the NSR-S620D, which is based on the new "Streamlign" platform was demonstrated. Last year's work focused mainly on machine evaluation data^[1]. Now, many S620Ds are employed at customers' sites and being used in device manufacturing. In this paper, the authors will introduce the latest factory data, as well as various techniques that enable superior yield and enhance productivity in IC manufacturing. It is well understood, that in order to achieve further device shrinks without using traditional techniques such as NA expansion or wavelength reduction, several practical issues must be overcome. Extremely tight overlay performance will be required for pitch splitting double patterning, for example. In addition, it is also necessary to control the image plane and the aberration of the optics much more carefully. Of course these improvements must also be achieved with sufficient productivity (throughput). In order to satisfy all of the requirements for mass production at customer factories, many variable factors must be dealt with. One of these variable factors is the characteristics of the processed wafers that include on-flatness, grid distortion, steep topology around the edge, or topography of the previous layers' patterns. These factors typically impact overlay and/or auto focus accuracy. Another variable is the difference in exposure conditions between layers, which include illumination conditions, dose, reticle transmittance, and the alignment marks. Exposure induced heating in particular is the key issue for today's enhanced throughput capabilities, with regards to achieving both optimal accuracy and productivity. In some IC production facilities, and often foundries, many different kinds of products are manufactured in parallel. However, in order to enhance performance and accuracy, it is sometimes necessary to optimize machine parameters for each product. Cleary this requires quick tuning capabilities to minimize overhead affects for each product. As discussed earlier, various techniques must be utilized to minimize the gap between machine inspection data and manufacturing performance at customer sites. This paper discusses such technologies and provides the supporting data.

In this paper we describe the basic principle of FlexWave, a new high resolution wavefront manipulator, and discuss experimental data on imaging, focus and overlay. For this we integrated the FlexWave module in a 1.35 NA immersion scanner. With FlexWave we can perform both static and dynamic wavefront corrections. Wavefront control with FlexWave minimizes lens aberrations under high productivity usage of the scanner, hence maintaining overlay and focus performance, but moreover, the high resolution wavefront tuning can be used to compensate for litho related effects. Especially now mask 3D effects are becoming a major error component, additional tuning is required. Optimized wavefront can be achieved with computational lithography, by either co-optimizing source, mask, and Wavefront Target prior to tape-out, or by tuning Wavefront Targets for specific masks and scanners after the reticle is made.

Source Mask Optimization¹ (SMO) is one of the most important techniques available for extending ArF immersion lithography. However, imaging with a small k1 factor (~0.3 or smaller) is very sensitive to errors in the imaging system, such as lens apodization, process control, mask error, etc. As a result, the real source shape must be re-adjusted to realize expected imaging performance as may be seen, for example, in an OPE curve. The intelligent illuminator can modify the pupilgram with high spatial and intensity resolution in the pupil. But the question is: How to adjust the pupilgram parameters properly to match target OPE? In this paper we present and describe a pupilgram adjusting method that can effectively control the various illuminator parameters. The method uses pupilgram modulation functions, which are similar to Zernike polynomials used in wavefront analysis, to describe the optimal pupilgram adjustment. The resulting modulation can then be realized by the intelligent illuminator. We demonstrate the effect of this method and the relation to minimum pupil resolution and gray scale levels that are needed for the intelligent illuminator to achieve its goals. In addition, a pupil analysis scheme, which is suitable for the applied pupilgram adjustment method, is proposed and validated. Using this method, SMO solutions will be more realistic and practically achievable for extending ArF immersion lithography.

IC manufacturers have a strong demand for transferring a working process from one scanner to another. Recently, a programmable illuminator (FlexRay^TM) became available on ASML ArF immersion scanners that, besides all the parameterized source shapes of the earlier Aerial^TM illuminator (based on diffractive optical elements) can also produce any desired freeform source shape. As a consequence, a fabrication environment may have scanners with each of the illuminator types so both FlexRay-to-Aerial and FlexRay-to-FlexRay matching is of interest. Moreover, the FlexRay illuminator itself is interesting from a matching point-of-view, as numerous degrees of freedom are added to the matching tuning space. This paper demonstrates how the upgrade of an exposure tool from Aerial to FlexRay illuminator shows identical proximity behavior without any need for scanner tuning. Also, an assessment of the imaging correspondence between exposure tools each equipped with a FlexRay illuminator is made. Finally, for a series of use-cases where proximity differences do exist, the application of FlexRay source tuning is demonstrated. It shows an enhancement of the scanner matching capabilities, because FlexRay source tuning enables matching where traditional NA and sigma tuning are shortcoming. Moreover, it enables tuning of freeform sources where sigma tuning is not relevant. Pattern Matcher^TM software of ASML Brion is demonstrated for the calculation of the optimized FlexRay tuned sources.

ArF immersion technology has been used widely in volume production for 45nm node. For 32nm node and beyond, double patterning technology with ArF immersion lithography is considered to be the main stream solution until EUV is ready. Our target is to reduce CoO(Cost of ownership) and we aim to develop for ecology and high durability laser. We will introduce the latest performance data of the laser built for ArF immersion lithography under the EcoPhoton concept. Eco-photon concept: -CoC (Cost of Consumable) -CoD (Cost of Downtime) -CoE(Cost of Energy & Environment) We have developed flexible and high power injection-lock ArF excimer laser for double patterning, GT62A-1SxE (Max90W/6000Hz/Flexible power with 10-15mJ/0.30pm (E95)) based on the GigaTwin platform5). A number of innovative and unique technologies are implemented on GT62A-1SxE. In addition, GT62A-1SxE is the laser matching the enhancement technology of advanced illumination systems. For example, in order to provide illumination power optimum for resist sensitivity, it has extendable power from 60W to 90W. We have confirmed durability under these concept with the regulated operation condition with flexible power 60-90W. We show the high durability data of GT62A-1SxE with Eco-Photon concept. In addition to the results the field reliability and availability of our Giga Twin series (GT6XA). We also show technologies which made these performances and its actual data. A number of innovative and unique technologies are implemented on GT62A.

For low k1 lithography the resolution of critical patterns on large designs can require advanced resolution enhancement techniques for masks including scattering bars, complicated mask edge segmentation and placement, etc. Often only a portion of a large layout will need this sophisticated mask design (the hotspot), with the remainder of layout being relatively simple for OPC methods to correct. In this paper we show how inverse lithography technology (ILT) can be used to correct selected regions of a large design after standard OPC has been used to correct the simple portions of the layout. The hotspot approach allows a computationally intensive ILT to be used in a limited way to correct the most difficult portions of a design. We will discuss the most important issues such as: model matching between ILT and OPC corrections; transition region corrections near the ILT and OPC boundary region; mask complexity; total combined runtime. We will show both simulated and actual wafer lithographic improvements in the hotspot regions.

The quadratic aberration model used in optical lithography is a natural extension of the linear model by taking into account interactions among individual Zernike coefficients. Although the model has been tested and verified in many applications, the effects of Zernike coefficients under partially coherent imaging are usually obtained by extensive experiments due to complexity of the model expression. In this paper, a generalized cross triple correlation (CTC) is introduced, and a fast algorithm to simulate the quadratic aberration model is developed. Simulations were performed by the proposed CTC based algorithm with different input Zernike aberrations for binary and phase shift masks with multiple pitches and orientations, which demonstrate that the proposed approach is not only accurate but also efficient for revealing the influence of different Zernike orders on aerial image intensity distributions under partially coherent illumination.

Inverse lithography which generates model-based patterns theoretically has superior patterning fidelity comparing to conventional rule-based technique. Cost functions are the determinant of performance inverse lithography that is also an optimization problem. However, the design and know-how of cost functions have rarely been discussed. In this paper, we investigate the impacts of various cost functions and their superposition for inverse lithography patterning exploiting a steepest descent algorithm. We research the most generally used objective functions, which are the resist and aerial images, and also deliver a derivation for the aerial image contrast. We then discuss the pattern fidelity and final mask characteristics for simple layouts with a single isolated contact and two nested contacts. Moreover, the convergences which are expressed by edge-placement error (EPE) and contrast versus iteration numbers rapidly attain to steady sate in most hybrid cost functions. All in all, we conclude that a cost function composed of a dominant resist-image component and a minor aerial-image or image-contrast component can carry out a good mask correction and contour targets when using inverse lithography patterning.

Completer polarimetry for immersion lithography equipment that comprises Stokes polarimetry of illumination and Mueller matrix polarimetry of projecting optics had been established. It was found that illumination and projecting optics were slightly different from our expectation. These differences might affect optical proximity correction and source mask optimization. However, no lithographer can desterilize parameter sets from the polarimetry for the use of lithography calculation because of their formats, Stokes parameters and Mueller matrix. Conventional lithography simulators require the Jones vector and Jones matrix only. When the illumination was partial polarization or the projecting optics was partially polarizing or partially depolarizing, the Jones calculus cannot support these situations. The Mueller calculus is needed for the case that involves polarizationdepolarization and depolarization-polarization translations. Previous works showed that actual un-polarization of illumination was somewhat polarized in the scan (y) direction and an actual catadioptric projecting optics has a little degrees of polarizance in the slit (x) direction. On the other hand, if you took the aberration effects into the lithography calculation, you had to use the Jones calculus. Therefore, for the lithography calculation with actual polarization data as well as actual aberration data, a special technique is required to handle these data. This paper describes how to physically convert Stokes parameters, which are multiplied by a general Mueller matrix, into Jones vectors. This method permits us to use the actual polarization data to the lithography calculation.

A self-aligned triple patterning (SATP) process is proposed to extend 193nm immersion lithography to half-pitch 15nm patterning. SATP process combines lithography and spacer techniques in a different manner than the conventional selfaligned double patterning (SADP) by keeping the mandrel lines and the second spacers. Compared with other scaling candidates such as self-aligned quadruple patterning (SAQP), it can relax the overlay accuracy requirement of critical layers and reduce their process complexity by using less masks. A 3-mask SATP mandrel recession (SMR) technique is invented to relax the overlay requirement of critical layer patterning. We also successfully demonstrate a 2-mask SATP process concept for patterning critical layers that contain lines/spaces, pads and peripheral circuits, thus opening an opportunity to significantly reduce the process costs. If applied in deep nano-scale IC fabrication, SATP technique will have a fundamental impact on the design methodology of integrated circuits. Using both dry and immersion lithography, we have fabricated half-pitch 21nm and 15nm patterns with a SATP process. It is found that the mandrels (lines) co-defined by lithography and etch processes have worse line width roughness (LWR) than that of spacers, which poses a unique problem to CD control in IC design. As a major focus of our early-stage research, patterning small mandrels/lines in SATP process is a non-trivial challenge. Different materials have been screened and an optimal scheme of mandrel and spacer materials is necessary to meet key requirements (e.g., LER and CDU) of the lithographic performance.

193nm immersion lithography, with the single-exposure resolution limitation of half-pitch 38nm, has extended its patterning capability to about 20nm using the double-patterning technique[1]. Despite the non-trivial sub-20nm patterning challenges, several NAND Flash manufacturers are already pursuing for sub-16nm patterning technology. 25nm NAND flash memory has already begun production in 2010, and given the typical 2-year scaling cycle, sub-16nm NAND devices should see pilot or mass production as early as 2014. Using novel patterning techniques such as sidewall spacer quadruple patterning (upon 120nm to 128nm pitch using dry ArF lithography) or triple patterning (upon 90nm pitch using immersion ArF lithography), we are able to extend optical lithography to sub-16nm half-pitch and demonstrate the lithographic performance that can nearly meet the ITRS roadmap requirements. In this paper, we conduct an in-depth review and demonstration of sidewall spacer quadruple patterning; including 300mm wafer level data of the mean values and CDU along with a mathematical assessment of the various data pools for sub-16nm lines and spaces. By understanding which processes (lithography, deposition, and etch) define the critical dimension of each data pool, we can make predictions of CDU capability for the sidewall spacer quad patterning. Our VeritySEM4i CD SEM tool demonstrated high measurement yield during fully automated measurements, which enables accurate lines, spaces and CDU measurements of the sub-16nm. The patterns generated from the sidewall spacer quadruple patterning techniques are used as a hardmask to transfer sub-16nm lines and spaces patterns to underneath amorphous silicon and silicon oxide layers, or poly silicon layer for 1X STI or poly gate applications.

The spacer defined double patterning (SDDP) approach for 20nm half pitch (HP) single damascene Cu interconnect structures using immersion lithography is being reviewed. Final results on wafer will be shown, focusing on critical double patterning topics such as CD & overlay budget and line edge roughness (LER); and their impact on the electrical functioning of the back-end-of-line test structures. The feasibility of extending the SDDP technique down to 15nm HP structures is also discussed. The 30nm line/space structures patterned in resist, required as a starting point for this exercise, will be patterned using EUV lithography.