23 March 2011 Full-chip source and mask optimization
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Proceedings Volume 7973, Optical Microlithography XXIV; 79730A (2011); doi: 10.1117/12.881633
Event: SPIE Advanced Lithography, 2011, San Jose, California, United States
Abstract
A cost-efficient technique for full-chip source and mask optimization is proposed in this paper. This technique has two components: SMO source optimization for full-chip and flexible mask optimization (FMO). During the technology development stage of source optimization, a novel pattern-selection technique was used to identify critical clips from a full-set of design clips; SMO was then used to optimize the source based on those selected critical-clips. This pattern-selection technique enables reasonable SMO runtime to optimize the source that covers the full range of patterns. During the process development stage and product tapeout stage, FMO is employed. The FMO framework allows the use of different OPC computational techniques on different chip areas that have different sensitivities to process variations. Advanced OPC methods are applied only where they are needed, therefore achieving optimum process performance with the least tapeout and mask cost.
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Min-Chun Tsai, Stephen Hsu, Luoqi Chen, Yen-Wen Lu, Jiangwei Li, Frank Chen, Hong Chen, Jun Tao, Been-Der Chen, Hanying Feng, William Wong, Wei Yuan, Xiaoyang Li, Zhipan Li, Liang Li, Russell Dover, Hua-yu Liu, Jim Koonmen, "Full-chip source and mask optimization", Proc. SPIE 7973, Optical Microlithography XXIV, 79730A (23 March 2011); doi: 10.1117/12.881633; http://dx.doi.org/10.1117/12.881633
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KEYWORDS
Source mask optimization

Photomasks

SRAF

Optical proximity correction

Lithography

Logic

Manufacturing

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