22 March 2011 Supreme lithographic performance by simple mask layout based on lithography and layout co-optimization
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Abstract
A method to resolve 20nm node of SRAM contact layer whose minimum pitch is 90nm with enough process latitude is shown. To achieve the target by single exposure under condition of ArF and 1.35 of NA a way to optimize lithography parameters and layout parameters simultaneously is applied that is called co-optimization. At first the memory cell is optimized from several viewpoints of device and lithography, and then the entire memory cell block including the array circuit is optimized. It proves that combination of co-optimization and insertion of SRAF works very well considering the appropriate printed shape required by the device layout. The co-optimization is compared to such a conventional method as OPC. The performance is better than conventional OPC. Especially the MEFF is much better and the evaluation to find the mechanism is shown. It proves that complex patterns with many fragments make MEEF higher. The superior characteristics of co-optimization are analyzed by the result of Linear Programming that can find the strict solution. The pixel source shape has become almost same as one by co-optimization. The solution is achieved by binary mask with simple patterns and the simple source shape. It is crucial for COO.
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Koichiro Tsujita, Koichiro Tsujita, Tadashi Arai, Tadashi Arai, Hiroyuki Ishii, Hiroyuki Ishii, Yuichi Gyoda, Yuichi Gyoda, Kazuhiro Takahashi, Kazuhiro Takahashi, Valery Axelrad, Valery Axelrad, Michael C. Smayling, Michael C. Smayling, } "Supreme lithographic performance by simple mask layout based on lithography and layout co-optimization", Proc. SPIE 7973, Optical Microlithography XXIV, 79730D (22 March 2011); doi: 10.1117/12.878663; https://doi.org/10.1117/12.878663
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