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22 March 2011 Towards manufacturing of advanced logic devices by double-patterning
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Abstract
As reported previously, the IBM Alliance has established a DETO (Double-Expose-Track-Optimized) baseline, in collaboration with ASML, TEL, and CNSE, to evaluate commercially available DETO photoresist system for the manufacturing of advanced logic devices. Although EUV lithography is the baseline strategy for <2x nm logic nodes, alternative techniques are still being pursued. The DETO technique produces pitch-split patterns capable of supporting 16 nm and 11 nm node semiconductor devices. We present the long-term monitoring performances of CD uniformity (CDU), overlay, and defectivity of our DETO process. CDU and overlay performances for controlled experiments are also presented. Two alignment schemes in DETO are compared experimentally for their effects on inter-level & intralevel overlays, and space CDU. We also experimented with methods for improving CDU, in which the CD-OptimizerTMand DoseMapperTM were evaluated separately and in tandem. Overlay improvements using the Correction Per Exposure (CPE) and the intra-field High-Order Process Correction (i-HOPC) were compared against the usual linear correction method. The effects of the exposure field size are also compared between a small field and the full field. Included in all the above, we also compare the performances derived from stack-integrated wafers and bare-Si wafers.
© (2011) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Chiew-seng Koay, Scott Halle, Steven Holmes, Karen Petrillo, Matthew Colburn, Youri van Dommelen, Aiqin Jiang, Michael Crouse, Shannon Dunn, David Hetzer, Shinichiro Kawakami, Jason Cantone, Lior Huli, Martin Rodgers, and Brian Martinick "Towards manufacturing of advanced logic devices by double-patterning", Proc. SPIE 7973, Optical Microlithography XXIV, 79730F (22 March 2011); https://doi.org/10.1117/12.879618
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