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22 March 2011 Spacer-defined double patterning for 20nm and beyond logic BEOL technology
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Abstract
Spacer-defined double patterning was investigated as a patterning option for 20/14-nm logic technology's back-end-of-line (BEOL), and compared with the double patterning options of front-end-of-line (FEOL). Negative spacer-defined double patterning was used to provide less overlay impact and variable CD control on the metal lines compared with other double patterning techniques. Block lithography as a 2nd exposure was able to maintain better tip-to-tip and tip-to-line fidelity by forming lines that behave as a additive etch block. SiO2 spacer was directly deposited on resist core-mandrel via a low-temperature deposition process. Resist integrity was optimized through aerial image and mask optimization as well as resist selection processes. Design decomposition of the BEOL layout was identified as a major challenge in enabling the spacer-defined double patterning. Finally, successful integration of the patterning into the BEOL device was demonstrated.
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Ryoung-Han Kim, Chiew-seng Koay, Sean D. Burns, Yunpeng Yin, John C. Arnold, Christopher Waskiewicz, Sanjay Mehta, Martin Burkhardt, Matthew E. Colburn, and Harry J. Levinson "Spacer-defined double patterning for 20nm and beyond logic BEOL technology", Proc. SPIE 7973, Optical Microlithography XXIV, 79730N (22 March 2011); https://doi.org/10.1117/12.881701
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