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22 March 2011 Enabling 22-nm logic node with advanced RET solutions
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The 22-nm technology node presents a real breakthrough compared to previous nodes in the way that state of the art scanner will be limited to a numerical aperture of 1.35. Thus we cannot "simply" apply a shrink factor from the previous node, and tradeoffs have to be found between Design Rules, Process integration and RET solutions in order to maintain the 50% density gain imposed by the Moore's law. One of the most challenging parts to enable the node is the ability to pattern Back-End Holes and Metal layers with sufficient process window. It is clearly established that early process for these layers will be performed by double patterning technique coupled with advanced OPC solutions. In this paper we propose a cross comparison between possible double patterning solutions: Pitch Splitting (PS) and Sidewall Image Transfer (SIT) and their implication on design rules and CD Uniformity. Advanced OPC solutions such as Model Based SRAF and Source Mask Optimization will also be investigated in order to ensure good process control. This work is a part of the Solid's JDP between ST, ASML and Brion in the framework of Nano2012 sponsored by the French government.
© (2011) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
V. Farys, L. Depre, J. Finders, V. Arnoux, Y. Trouiller, H. Y. Liu, E. Yesilada, N. Zeggaoui, and C. Alleaume "Enabling 22-nm logic node with advanced RET solutions", Proc. SPIE 7973, Optical Microlithography XXIV, 79730T (22 March 2011);

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