23 March 2011 3D lithography modeling for ground rule development
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Proceedings Volume 7973, Optical Microlithography XXIV; 797315 (2011); doi: 10.1117/12.879213
Event: SPIE Advanced Lithography, 2011, San Jose, California, United States
Abstract
The ability to incorporate the effect of patterned underlayers in a 3-dimensional physical resist model that truly mimics the process on real wafers could be used to formulate robust ground rules for design. We have shown as an example block level simulations, where the resist critical dimension is determined by the presence of STI (shallow trench isolation) and/or patterned gate level underneath & their relative spacing, as confirmed on wafer. We will demonstrate how the results of such study could be used for creating ground rules which are truly dependent on the interaction between the current layer resist & the patterned layers underneath. We have also developed a new way to visualize lithographic process variations in 3-D space that is useful for simulation analysis that can prove very helpful in ground rule development and process optimization. Such visualization capability in the dataprep flow to flag issues or dispose critical structures increases speed and efficiency in the mask tapeout process.
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Chandra Sarma, Todd Bailey, Adam Lyons, Dongbing Shao, "3D lithography modeling for ground rule development", Proc. SPIE 7973, Optical Microlithography XXIV, 797315 (23 March 2011); doi: 10.1117/12.879213; https://doi.org/10.1117/12.879213
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KEYWORDS
3D modeling

Semiconducting wafers

Photoresist processing

Critical dimension metrology

Silicon

Photovoltaics

Lithography

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