You have requested a machine translation of selected content from our databases. This functionality is provided solely for your convenience and is in no way intended to replace human translation. Neither SPIE nor the owners and publishers of the content make, and they explicitly disclaim, any express or implied representations or warranties of any kind, including, without limitation, representations and warranties as to the functionality of the translation feature or the accuracy or completeness of the translations.
Translations are not retained in our system. Your use of this feature and the translations is subject to all use restrictions contained in the Terms and Conditions of Use of the SPIE website.
22 March 2011Mask enhancer technology with source mask optimization (SMO) for 2Xnm-node logic layout gate fabrication
Strong resolution enhancement technologies (RETs) combined with hyper-NA
ArF immersion lithography with source and mask optimization (SMO) have become
necessary to achieve sufficient resolution in 2Xnm node devices. Conventional SMO
methods have focused on minimizing the edge placement error and/or the cost functions
of dose, focus, and mask errors. This has not, however, resolved the conflict between line
and gap patterns on logic gate layouts. One issue remaining in particular is the mask error
enhancement factor (MEEF). Furthermore, the pattern shapes at the line end gaps of
SRAM gates remain a major challenge for logic device manufacturers. To overcome
these problems, we explain the importance of controlling the light intensity profiles at
line end gaps, focusing on a Panasonic product called "Mask Enhancer" that comprises
an attenuated mask with a phase shifting aperture and enables light intensity profiles to be
controlled easily. We demonstrate the product's effectiveness in printing gates with
optimized illumination source shapes. A simulation experiment and a feasibility study
confirmed that Mask Enhancer can improve the MEEF and pattern shapes at the line ends
of SRAM gates.