193nm immersion lithography, with the single-exposure resolution limitation of half-pitch 38nm, has extended its
patterning capability to about 20nm using the double-patterning technique. Despite the non-trivial sub-20nm
patterning challenges, several NAND Flash manufacturers are already pursuing for sub-16nm patterning technology.
25nm NAND flash memory has already begun production in 2010, and given the typical 2-year scaling cycle, sub-16nm
NAND devices should see pilot or mass production as early as 2014. Using novel patterning techniques such as sidewall
spacer quadruple patterning (upon 120nm to 128nm pitch using dry ArF lithography) or triple patterning (upon 90nm
pitch using immersion ArF lithography), we are able to extend optical lithography to sub-16nm half-pitch and
demonstrate the lithographic performance that can nearly meet the ITRS roadmap requirements.
In this paper, we conduct an in-depth review and demonstration of sidewall spacer quadruple patterning; including
300mm wafer level data of the mean values and CDU along with a mathematical assessment of the various data pools for
sub-16nm lines and spaces. By understanding which processes (lithography, deposition, and etch) define the critical
dimension of each data pool, we can make predictions of CDU capability for the sidewall spacer quad patterning. Our
VeritySEM4i CD SEM tool demonstrated high measurement yield during fully automated measurements, which enables
accurate lines, spaces and CDU measurements of the sub-16nm. The patterns generated from the sidewall spacer
quadruple patterning techniques are used as a hardmask to transfer sub-16nm lines and spaces patterns to underneath
amorphous silicon and silicon oxide layers, or poly silicon layer for 1X STI or poly gate applications.