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22 March 2011 Study of various RET for process margin improvement in 3Xnm DRAM contact
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As the DRAM node shrinks down to its natural limit, photo lithography is encountering many difficulties. 3Xnm DRAM node seems to be the limit for ArF Immersion. Until the arrival of EUV, double patterning (DPT) or spacer double patterning (SPT) seems like the next solution. But the problem with DPT or SPT is that both increases process step their by increasing the final costs of the device. So limiting the use of DPT or SPT is very important for device fabrication. For 3Xnm DRAM, storage node is one of the candidates to eliminate DPT or SPT process. But this method may cost lower process margin and degradation of pattern image. So, solution to these problems is very crucial. In this study, we will realize storage node (SN) pattern for 3Xnm DRAM node with improved process margin. First we will discuss selection of illumination for optimal condition second, correction of the mask will be introduced. We will also talk about the usage of various RET such as model based assist feature. Value such as DOF, EL and CDU (critical dimension uniformity) will be evaluated and analyzed.
© (2011) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Hak-Yong Sim, Hyoung-Soon Yune, Yeong-Bae Ahn, James Moon, Byoung-Sub Nam, Donggyu Yim, and Sung-Ki Park "Study of various RET for process margin improvement in 3Xnm DRAM contact", Proc. SPIE 7973, Optical Microlithography XXIV, 79732N (22 March 2011);


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