29 March 2011 Moore's Law in the innovation era
Author Affiliations +
Abstract
Traditional transistor scaling methods served our industry well for more than three decades until the early 1990s when leakage current and active power constraints threatened to end the continued improvements provided by Moore's Law. The end of the traditional scaling era ushered in the beginning of the innovation era. Process technology innovations such as strained silicon, high-k metal gate transistors, and copper + low-k interconnects have enabled continued performance improvements for scaled devices. Microprocessor design and architecture innovations such as multi-core designs combined with power gates were significant contributors to improved performance and improved power efficiency. Future computing products demand small form factors and long battery life that can be met through a combination of transistor innovation, System-on-Chip and System-in-Package integration techniques.
© (2011) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Mark Bohr, Mark Bohr, } "Moore's Law in the innovation era", Proc. SPIE 7974, Design for Manufacturability through Design-Process Integration V, 797402 (29 March 2011); doi: 10.1117/12.883462; https://doi.org/10.1117/12.883462
PROCEEDINGS
8 PAGES


SHARE
RELATED CONTENT

3D-ICs created using oblique processing
Proceedings of SPIE (March 21 2016)
Heterogeneous integration of low-temperature metal-oxide TFTs
Proceedings of SPIE (February 24 2017)
Technology in the Internet era
Proceedings of SPIE (August 20 2001)
Integrated process for smart microstructures
Proceedings of SPIE (May 20 1996)
SiGe/Si vertical PMOSFET device design and fabrication
Proceedings of SPIE (August 27 1997)
Highly manufacturable capacitor-less 1T-DRAM concept
Proceedings of SPIE (July 12 2002)

Back to Top