Lithographic variation aware design centering for SRAM yield enhancement

Kanak Agarwal

doi:10.1117/12.879503

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4 April 2011 Lithographic variation aware design centering for SRAM yield enhancement

Kanak Agarwal

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Proceedings Volume 7974, Design for Manufacturability through Design-Process Integration V; 797406 (2011) https://doi.org/10.1117/12.879503
Event: SPIE Advanced Lithography, 2011, San Jose, California, United States

Abstract

Static Random Access Memory (SRAM) cells use the smallest manufacturable device sizes in a given technology and hence see a highly pronounced random dopant effect. Moreover, SRAM cells are designed to satisfy conflicting read and write requirements. It makes SRAMs extremely vulnerable to failures due to lithographic variations. We propose a design centering approach for maximizing SRAM electrical yield under lithographic variation. The centering is obtained by applying small biases to the gate lengths of devices in the circuit. We refer to this process of enhancing electrical yield by changing the original target layout as electrically driven layout retargeting. The idea behind layout retargeting is that the default distribution of process variability band (PV-band) around nominal design edge is sub-optimal for electrical yield. The overall worst-case electrical yield can be improved by intentional shifting of the lithographic PV-band in the preferred direction. The PV-band can be shifted through retargeting the layout such that nominal target CD is biased up or down to obtain a desired shift. We present a linear programming formulation to calculate the optimal retargeting values for each device in the circuit. We apply the proposed retargeting flow to optimize electrical yield of an industrial SRAM design. Our results show that the electrically driven retargeting scheme improves the normalized SRAM yield from 0.89 (read access yield at outer lithographic contour) to 0.95 (read disturb yield at inner contour).

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Kanak Agarwal "Lithographic variation aware design centering for SRAM yield enhancement", Proc. SPIE 7974, Design for Manufacturability through Design-Process Integration V, 797406 (4 April 2011); https://doi.org/10.1117/12.879503

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