4 April 2011 Applying litho-aware timing analysis to hold time fixing reduces design cycle time and power dissipation
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Abstract
In this paper, we present an innovative approach to reduce power and accelerate timing closure by using simulated silicon-calibrated contours to predict the litho effects on transistor gates and perform litho-aware critical paths analysis. This approach is used to filter the false hold time violations and focus designers' actions on the most relevant violations. After silicon validation, the application of this technique to hold time fixing on a 90nm micro-controller unit product reduces the power increase and runtime of the hold buffer insertion. This study not only demonstrates the feasibility of the Litho-aware STA flow but also shows its value to reduce hold time fixing effort and power dissipation caused by buffer insertion.
© (2011) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Keisuke Hirabayashi, Keisuke Hirabayashi, Naohiro Kobayashi, Naohiro Kobayashi, Hidemichi Mizuno, Hidemichi Mizuno, Tomoo Onodera, Tomoo Onodera, Tsuyoshi Oguro, Tsuyoshi Oguro, Philippe Hurat, Philippe Hurat, Arindam Chatterjee, Arindam Chatterjee, Koichi Seki, Koichi Seki, } "Applying litho-aware timing analysis to hold time fixing reduces design cycle time and power dissipation", Proc. SPIE 7974, Design for Manufacturability through Design-Process Integration V, 797408 (4 April 2011); doi: 10.1117/12.878695; https://doi.org/10.1117/12.878695
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