As the optical lithography advances into the sub-30nm technology node, many candidates of the lithography have been
discussed. Double pattering technology (DPT) has been a primary lithography candidate for the direct contact of the
sub-30nm device due to a merit of a low mask cost and process stability compared to the extreme ultraviolet lithography
(EUV). However, the major concerns of DPT are the critical dimension (CD) skew and overlay error between the 1st and
2nd pattering, which cause the degradation of electrical performance such as the mismatch of the pair transistors of the
analog circuit. If we assume there is the 10nm position difference of the direct contact between the pair transistors, which
is induced by the overlay error between the 1st and 2nd pattering of the DPT process, then the threshold voltage difference
between the pair transistors is about 10%. Therefore, the direct contact of the pair transistors must be decomposed as the
same color to minimize the threshold voltage variation of the analog circuit. Since the DPT process of the direct contact
is the litho-etch-litho-etch (LELE) process, there are the CD variations induced by the global density difference between
the 1st and 2nd mask.
In this paper, we newly develop the DPT methodology to decompose the direct contact of the pair transistors to the
same mask using the optimized marking polygons, decomposition algorithm. In addition, the decomposition algorithm
for the density balancing between the 1st and 2nd mask is developed to minimize the CD variations caused by the density
difference. Our main contributions are as follows. (1) The optimal marking polygons, which group the direct contacts of
the pair transistors, are designed to consider the layout configurations of pair transistors. The space between each contact
located on the same marking polygon is designed to be larger than the resolution limit of the single exposure, so that the
contacts grouped by the same marking polygon can be decomposed as the same color. (2) The whole contacts grouped
by the same marking polygon are changed to the representative single contact, and then the colors of the grouped
contacts are assigned by the representative single contact and its surrounded contacts. (3) After decomposing the layout
to consider the contact on the pair transistors, the remaining contacts, which is not necessary to decompose from the
view point of the patterning limit, are decomposed to satisfy the density balance between the 1st and 2nd mask.
Consequently, we can achieve the pattering margin and electrical performance of sub-30nm device by applying the new
DPT methodology to the direct contact.