The traditional design rule paradigm of defining the illegal areas of the design space has been deteriorating at the
advanced technology nodes. Radical design space restrictions, advocated by the regular design fabrics methodology,
provide an opportunity to reshape the design/manufacturing interface by constraining the layout to a set of allowable
patterns. As such, this would allow for guaranteed convergence of the source mask optimization techniques (SMO) and
complete validation of the legal design space during technology development and ramp. However, the number of the
unique patterns generated by the layout adhering to even the simplistic gridded design rules prohibits this approach.
Nevertheless, we have found that just 10% of the unique geometric patterns are sufficient to represent 90% of all layout
pattern instances. Furthermore, the overall number of layout patterns on Active, Contact, and Metal-1 design layers can
be reduced through modification of existing layout shapes in the final layout database and insertion of non-essential
layout features. Unlike the 'dummy fill' used for chemical mechanical polishing (CMP), the newly added shapes must
resemble the patterning of the functional design features and be inserted in close proximity to them. In this paper, we
evaluate the digital circuit performance impact of the additional layout parasitics introduced by these 'dummy' features.
In particular, we have found that a significant pattern count reduction can be achieved with minimal performance
penalty. These results have been used at PDF Solutions to enable a correct by construction layout style, such as the
templates and connectors-based layout methodology presented in the companion paper.