4 April 2011 Layout decomposition of self-aligned double patterning for 2D random logic patterning
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Abstract
Self-aligned double pattering (SADP) has been adapted as a promising solution for sub-30nm technology nodes due to its lower overlay problem and better process tolerance. SADP is in production use for 1D dense patterns with good pitch control such as NAND Flash memory applications, but it is still challenging to apply SADP to 2D random logic patterns. The favored type of SADP for complex logic interconnects is a two mask approach using a core mask and a trim mask. In this paper, we first describe layout decomposition methods of spacer-type double patterning lithography, then report a type of SADP compliant layouts, and finally report SADP applications on Samsung 22nm SRAM layout. For SADP decomposition, we propose several SADP-aware layout coloring algorithms and a method of generating lithography-friendly core mask patterns. Experimental results on 22nm node designs show that our proposed layout decomposition for SADP effectively decomposes any given layouts.
© (2011) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Yongchan Ban, Yongchan Ban, Alex Miloslavsky, Alex Miloslavsky, Kevin Lucas, Kevin Lucas, Soo-Han Choi, Soo-Han Choi, Chul-Hong Park, Chul-Hong Park, David Z. Pan, David Z. Pan, } "Layout decomposition of self-aligned double patterning for 2D random logic patterning", Proc. SPIE 7974, Design for Manufacturability through Design-Process Integration V, 79740L (4 April 2011); doi: 10.1117/12.879500; https://doi.org/10.1117/12.879500
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