Amongst the possible double patterning strategies for sub 32nm processes, self-aligned double patterning
(SADP) has moved from Flash-only processes to more general purpose devices. The reason is that while litho-etch-
litho-etc (LELE) process was originally preferred due to its simplicity and relative low cost, its sensitivity
to overlay error has prompted the search for other methods.
Although the basic SADP process is fairly robust against the overlay error, the robustness of 2D SADP
method strongly depends on layout and decomposition styles and decomposability compliance. In this paper,
we first discuss different printability challenges for SADP method. Afterward, we propose a SADP-aware
detailed routing method, by applying a correct-by-construction approach, to provide SADP-friendly layouts.
This method performs detailed routing and layout decomposition concurrently to prevent litho-limited layout
configurations. Experimental results show that, compared with a SADP-blind detailed router, the proposed
method achieves considerable robustness against lithography imperfection in expense of tolerable wire length