In IC manufacturing, the performance of standard cells often varies due to process non-idealities. Some research
work on 2-D cell characterization shows that the timing variations can be characterized by the timing model.
However, as regular design rules become necessary in sub-45nm node circuit design, 1-D design has shown its
advantages and has drawn intensive research interest. The circuit performance of a 1-D standard cell can be more
accurately predicted than that of a 2-D standard cell as it is insensitive to layout context. This paper presents
a characterization methodology to predict the delay and power performance of 1-D standard cells. We perform
lithography simulation on the poly gate array generated by dense line printing technology, which constructs the
poly gates of inverters, and do statistical analysis on the data simulated within the process window. After that,
circuit simulation is performed on the printed cell to obtain its delay and power performance, and the delay
and power distribution curves are generated, which accurately predict the circuit performance of standard cells.
In the end, the benefits of our cell characterization method are analyzed from both design and manufacturing
perspectives, which shows great advantages in accurate circuit analysis and yield improving.