13 April 2011 A new architecture for designing noise-tolerant digital circuits
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Abstract
Defects and faults arise from physical imperfections and noise susceptibility of the analog circuit components used to create digital circuits resulting in computational errors. A probabilistic computational model is needed to quantify and analyze the effect of noisy signals on computational accuracy in digital circuits. This model computes the reliability of digital circuits meaning that the inputs and outputs and their implemented logic function need to be calculated probabilistically. The purpose of this paper is to present a new architecture for designing noise-tolerant digital circuits. The approach we propose is to use a class of single-input, single-output circuits called Reliability Enhancement Network Chain (RENC). A RENC is a concatenation of n simple logic circuits called Reliability Enhancement Network (REN). Each REN can increase the reliability of a digital circuit to a higher level. Reliability of the circuit can approach any desirable level when a RENC composed of a sufficient number of RENs is employed. Moreover, the proposed approach is applicable to the design of any logic circuit implemented with any logic technology.
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Jeremy M. Lakes, Jeremy M. Lakes, Samuel C. Lee, Samuel C. Lee, } "A new architecture for designing noise-tolerant digital circuits", Proc. SPIE 7980, Nanosensors, Biosensors, and Info-Tech Sensors and Systems 2011, 79800J (13 April 2011); doi: 10.1117/12.880304; https://doi.org/10.1117/12.880304
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